1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on da830evm.c. Original Copyrights follow: 5 * 6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #include <common.h> 25 #include <i2c.h> 26 #include <net.h> 27 #include <netdev.h> 28 #include <asm/arch/hardware.h> 29 #include <asm/arch/emif_defs.h> 30 #include <asm/arch/emac_defs.h> 31 #include <asm/io.h> 32 #include <asm/arch/davinci_misc.h> 33 #include <hwconfig.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) 38 39 /* SPI0 pin muxer settings */ 40 static const struct pinmux_config spi1_pins[] = { 41 { pinmux(5), 1, 1 }, 42 { pinmux(5), 1, 2 }, 43 { pinmux(5), 1, 4 }, 44 { pinmux(5), 1, 5 } 45 }; 46 47 /* UART pin muxer settings */ 48 static const struct pinmux_config uart_pins[] = { 49 { pinmux(0), 4, 6 }, 50 { pinmux(0), 4, 7 }, 51 { pinmux(4), 2, 4 }, 52 { pinmux(4), 2, 5 } 53 }; 54 55 #ifdef CONFIG_DRIVER_TI_EMAC 56 static const struct pinmux_config emac_pins[] = { 57 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 58 { pinmux(14), 8, 2 }, 59 { pinmux(14), 8, 3 }, 60 { pinmux(14), 8, 4 }, 61 { pinmux(14), 8, 5 }, 62 { pinmux(14), 8, 6 }, 63 { pinmux(14), 8, 7 }, 64 { pinmux(15), 8, 1 }, 65 #else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */ 66 { pinmux(2), 8, 1 }, 67 { pinmux(2), 8, 2 }, 68 { pinmux(2), 8, 3 }, 69 { pinmux(2), 8, 4 }, 70 { pinmux(2), 8, 5 }, 71 { pinmux(2), 8, 6 }, 72 { pinmux(2), 8, 7 }, 73 { pinmux(3), 8, 0 }, 74 { pinmux(3), 8, 1 }, 75 { pinmux(3), 8, 2 }, 76 { pinmux(3), 8, 3 }, 77 { pinmux(3), 8, 4 }, 78 { pinmux(3), 8, 5 }, 79 { pinmux(3), 8, 6 }, 80 { pinmux(3), 8, 7 }, 81 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ 82 { pinmux(4), 8, 0 }, 83 { pinmux(4), 8, 1 } 84 }; 85 86 /* I2C pin muxer settings */ 87 static const struct pinmux_config i2c_pins[] = { 88 { pinmux(4), 2, 2 }, 89 { pinmux(4), 2, 3 } 90 }; 91 92 #ifdef CONFIG_NAND_DAVINCI 93 const struct pinmux_config nand_pins[] = { 94 { pinmux(7), 1, 1 }, 95 { pinmux(7), 1, 2 }, 96 { pinmux(7), 1, 4 }, 97 { pinmux(7), 1, 5 }, 98 { pinmux(9), 1, 0 }, 99 { pinmux(9), 1, 1 }, 100 { pinmux(9), 1, 2 }, 101 { pinmux(9), 1, 3 }, 102 { pinmux(9), 1, 4 }, 103 { pinmux(9), 1, 5 }, 104 { pinmux(9), 1, 6 }, 105 { pinmux(9), 1, 7 }, 106 { pinmux(12), 1, 5 }, 107 { pinmux(12), 1, 6 } 108 }; 109 #elif defined(CONFIG_USE_NOR) 110 /* NOR pin muxer settings */ 111 const struct pinmux_config nor_pins[] = { 112 /* GP0[11] is required for NOR to work on Rev 3 EVMs */ 113 { pinmux(0), 8, 4 }, /* GP0[11] */ 114 { pinmux(5), 1, 6 }, 115 { pinmux(6), 1, 6 }, 116 { pinmux(7), 1, 0 }, 117 { pinmux(7), 1, 4 }, 118 { pinmux(7), 1, 5 }, 119 { pinmux(8), 1, 0 }, 120 { pinmux(8), 1, 1 }, 121 { pinmux(8), 1, 2 }, 122 { pinmux(8), 1, 3 }, 123 { pinmux(8), 1, 4 }, 124 { pinmux(8), 1, 5 }, 125 { pinmux(8), 1, 6 }, 126 { pinmux(8), 1, 7 }, 127 { pinmux(9), 1, 0 }, 128 { pinmux(9), 1, 1 }, 129 { pinmux(9), 1, 2 }, 130 { pinmux(9), 1, 3 }, 131 { pinmux(9), 1, 4 }, 132 { pinmux(9), 1, 5 }, 133 { pinmux(9), 1, 6 }, 134 { pinmux(9), 1, 7 }, 135 { pinmux(10), 1, 0 }, 136 { pinmux(10), 1, 1 }, 137 { pinmux(10), 1, 2 }, 138 { pinmux(10), 1, 3 }, 139 { pinmux(10), 1, 4 }, 140 { pinmux(10), 1, 5 }, 141 { pinmux(10), 1, 6 }, 142 { pinmux(10), 1, 7 }, 143 { pinmux(11), 1, 0 }, 144 { pinmux(11), 1, 1 }, 145 { pinmux(11), 1, 2 }, 146 { pinmux(11), 1, 3 }, 147 { pinmux(11), 1, 4 }, 148 { pinmux(11), 1, 5 }, 149 { pinmux(11), 1, 6 }, 150 { pinmux(11), 1, 7 }, 151 { pinmux(12), 1, 0 }, 152 { pinmux(12), 1, 1 }, 153 { pinmux(12), 1, 2 }, 154 { pinmux(12), 1, 3 }, 155 { pinmux(12), 1, 4 }, 156 { pinmux(12), 1, 5 }, 157 { pinmux(12), 1, 6 }, 158 { pinmux(12), 1, 7 } 159 }; 160 #endif 161 162 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 163 #define HAS_RMII 1 164 #else 165 #define HAS_RMII 0 166 #endif 167 #endif /* CONFIG_DRIVER_TI_EMAC */ 168 169 void dsp_lpsc_on(unsigned domain, unsigned int id) 170 { 171 dv_reg_p mdstat, mdctl, ptstat, ptcmd; 172 struct davinci_psc_regs *psc_regs; 173 174 psc_regs = davinci_psc0_regs; 175 mdstat = &psc_regs->psc0.mdstat[id]; 176 mdctl = &psc_regs->psc0.mdctl[id]; 177 ptstat = &psc_regs->ptstat; 178 ptcmd = &psc_regs->ptcmd; 179 180 while (*ptstat & (0x1 << domain)) 181 ; 182 183 if ((*mdstat & 0x1f) == 0x03) 184 return; /* Already on and enabled */ 185 186 *mdctl |= 0x03; 187 188 *ptcmd = 0x1 << domain; 189 190 while (*ptstat & (0x1 << domain)) 191 ; 192 while ((*mdstat & 0x1f) != 0x03) 193 ; /* Probably an overkill... */ 194 } 195 196 static void dspwake(void) 197 { 198 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; 199 u32 val; 200 201 /* if the device is ARM only, return */ 202 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) 203 return; 204 205 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) 206 return; 207 208 *resetvect++ = 0x1E000; /* DSP Idle */ 209 /* clear out the next 10 words as NOP */ 210 memset(resetvect, 0, sizeof(unsigned) *10); 211 212 /* setup the DSP reset vector */ 213 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); 214 215 dsp_lpsc_on(1, DAVINCI_LPSC_GEM); 216 val = readl(PSC0_MDCTL + (15 * 4)); 217 val |= 0x100; 218 writel(val, (PSC0_MDCTL + (15 * 4))); 219 } 220 221 int misc_init_r(void) 222 { 223 dspwake(); 224 return 0; 225 } 226 227 static const struct pinmux_resource pinmuxes[] = { 228 #ifdef CONFIG_SPI_FLASH 229 PINMUX_ITEM(spi1_pins), 230 #endif 231 PINMUX_ITEM(uart_pins), 232 PINMUX_ITEM(i2c_pins), 233 #ifdef CONFIG_NAND_DAVINCI 234 PINMUX_ITEM(nand_pins), 235 #elif defined(CONFIG_USE_NOR) 236 PINMUX_ITEM(nor_pins), 237 #endif 238 }; 239 240 static const struct lpsc_resource lpsc[] = { 241 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ 242 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ 243 { DAVINCI_LPSC_EMAC }, /* image download */ 244 { DAVINCI_LPSC_UART2 }, /* console */ 245 { DAVINCI_LPSC_GPIO }, 246 }; 247 248 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK 249 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 250 #endif 251 252 /* 253 * get_board_rev() - setup to pass kernel board revision information 254 * Returns: 255 * bit[0-3] Maximum cpu clock rate supported by onboard SoC 256 * 0000b - 300 MHz 257 * 0001b - 372 MHz 258 * 0010b - 408 MHz 259 * 0011b - 456 MHz 260 */ 261 u32 get_board_rev(void) 262 { 263 char *s; 264 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; 265 u32 rev = 0; 266 267 s = getenv("maxcpuclk"); 268 if (s) 269 maxcpuclk = simple_strtoul(s, NULL, 10); 270 271 if (maxcpuclk >= 456000000) 272 rev = 3; 273 else if (maxcpuclk >= 408000000) 274 rev = 2; 275 else if (maxcpuclk >= 372000000) 276 rev = 1; 277 278 return rev; 279 } 280 281 int board_init(void) 282 { 283 #ifdef CONFIG_USE_NOR 284 u32 val; 285 #endif 286 287 #ifndef CONFIG_USE_IRQ 288 irq_init(); 289 #endif 290 291 #ifdef CONFIG_NAND_DAVINCI 292 /* 293 * NAND CS setup - cycle counts based on da850evm NAND timings in the 294 * Linux kernel @ 25MHz EMIFA 295 */ 296 writel((DAVINCI_ABCR_WSETUP(0) | 297 DAVINCI_ABCR_WSTROBE(1) | 298 DAVINCI_ABCR_WHOLD(0) | 299 DAVINCI_ABCR_RSETUP(0) | 300 DAVINCI_ABCR_RSTROBE(1) | 301 DAVINCI_ABCR_RHOLD(0) | 302 DAVINCI_ABCR_TA(1) | 303 DAVINCI_ABCR_ASIZE_8BIT), 304 &davinci_emif_regs->ab2cr); /* CS3 */ 305 #endif 306 307 /* arch number of the board */ 308 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; 309 310 /* address of boot parameters */ 311 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; 312 313 /* 314 * Power on required peripherals 315 * ARM does not have access by default to PSC0 and PSC1 316 * assuming here that the DSP bootloader has set the IOPU 317 * such that PSC access is available to ARM 318 */ 319 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) 320 return 1; 321 322 /* setup the SUSPSRC for ARM to control emulation suspend */ 323 writel(readl(&davinci_syscfg_regs->suspsrc) & 324 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | 325 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | 326 DAVINCI_SYSCFG_SUSPSRC_UART2), 327 &davinci_syscfg_regs->suspsrc); 328 329 /* configure pinmux settings */ 330 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) 331 return 1; 332 333 #ifdef CONFIG_USE_NOR 334 /* Set the GPIO direction as output */ 335 clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); 336 337 /* Set the output as low */ 338 val = readl(GPIO_BANK0_REG_SET_ADDR); 339 val |= (0x01 << 11); 340 writel(val, GPIO_BANK0_REG_CLR_ADDR); 341 #endif 342 343 #ifdef CONFIG_DRIVER_TI_EMAC 344 if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) 345 return 1; 346 347 davinci_emac_mii_mode_sel(HAS_RMII); 348 #endif /* CONFIG_DRIVER_TI_EMAC */ 349 350 /* enable the console UART */ 351 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 352 DAVINCI_UART_PWREMU_MGMT_UTRST), 353 &davinci_uart2_ctrl_regs->pwremu_mgmt); 354 355 return 0; 356 } 357 358 #ifdef CONFIG_DRIVER_TI_EMAC 359 360 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 361 /** 362 * rmii_hw_init 363 * 364 * DA850/OMAP-L138 EVM can interface to a daughter card for 365 * additional features. This card has an I2C GPIO Expander TCA6416 366 * to select the required functions like camera, RMII Ethernet, 367 * character LCD, video. 368 * 369 * Initialization of the expander involves configuring the 370 * polarity and direction of the ports. P07-P05 are used here. 371 * These ports are connected to a Mux chip which enables only one 372 * functionality at a time. 373 * 374 * For RMII phy to respond, the MII MDIO clock has to be disabled 375 * since both the PHY devices have address as zero. The MII MDIO 376 * clock is controlled via GPIO2[6]. 377 * 378 * This code is valid for Beta version of the hardware 379 */ 380 int rmii_hw_init(void) 381 { 382 const struct pinmux_config gpio_pins[] = { 383 { pinmux(6), 8, 1 } 384 }; 385 u_int8_t buf[2]; 386 unsigned int temp; 387 int ret; 388 389 /* PinMux for GPIO */ 390 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) 391 return 1; 392 393 /* I2C Exapnder configuration */ 394 /* Set polarity to non-inverted */ 395 buf[0] = 0x0; 396 buf[1] = 0x0; 397 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); 398 if (ret) { 399 printf("\nExpander @ 0x%02x write FAILED!!!\n", 400 CONFIG_SYS_I2C_EXPANDER_ADDR); 401 return ret; 402 } 403 404 /* Configure P07-P05 as outputs */ 405 buf[0] = 0x1f; 406 buf[1] = 0xff; 407 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); 408 if (ret) { 409 printf("\nExpander @ 0x%02x write FAILED!!!\n", 410 CONFIG_SYS_I2C_EXPANDER_ADDR); 411 } 412 413 /* For Ethernet RMII selection 414 * P07(SelA)=0 415 * P06(SelB)=1 416 * P05(SelC)=1 417 */ 418 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 419 printf("\nExpander @ 0x%02x read FAILED!!!\n", 420 CONFIG_SYS_I2C_EXPANDER_ADDR); 421 } 422 423 buf[0] &= 0x1f; 424 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); 425 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 426 printf("\nExpander @ 0x%02x write FAILED!!!\n", 427 CONFIG_SYS_I2C_EXPANDER_ADDR); 428 } 429 430 /* Set the output as high */ 431 temp = REG(GPIO_BANK2_REG_SET_ADDR); 432 temp |= (0x01 << 6); 433 REG(GPIO_BANK2_REG_SET_ADDR) = temp; 434 435 /* Set the GPIO direction as output */ 436 temp = REG(GPIO_BANK2_REG_DIR_ADDR); 437 temp &= ~(0x01 << 6); 438 REG(GPIO_BANK2_REG_DIR_ADDR) = temp; 439 440 return 0; 441 } 442 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ 443 444 /* 445 * Initializes on-board ethernet controllers. 446 */ 447 int board_eth_init(bd_t *bis) 448 { 449 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 450 /* Select RMII fucntion through the expander */ 451 if (rmii_hw_init()) 452 printf("RMII hardware init failed!!!\n"); 453 #endif 454 if (!davinci_emac_initialize()) { 455 printf("Error: Ethernet init failed!\n"); 456 return -1; 457 } 458 459 return 0; 460 } 461 #endif /* CONFIG_DRIVER_TI_EMAC */ 462