1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on da830evm.c. Original Copyrights follow: 5 * 6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #include <common.h> 25 #include <i2c.h> 26 #include <net.h> 27 #include <netdev.h> 28 #include <spi.h> 29 #include <spi_flash.h> 30 #include <asm/arch/hardware.h> 31 #include <asm/arch/emif_defs.h> 32 #include <asm/arch/emac_defs.h> 33 #include <asm/arch/pinmux_defs.h> 34 #include <asm/io.h> 35 #include <asm/arch/davinci_misc.h> 36 #include <asm/errno.h> 37 #include <hwconfig.h> 38 39 #ifdef CONFIG_DAVINCI_MMC 40 #include <mmc.h> 41 #include <asm/arch/sdmmc_defs.h> 42 #endif 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 #ifdef CONFIG_DRIVER_TI_EMAC 47 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 48 #define HAS_RMII 1 49 #else 50 #define HAS_RMII 0 51 #endif 52 #endif /* CONFIG_DRIVER_TI_EMAC */ 53 54 #define CFG_MAC_ADDR_SPI_BUS 0 55 #define CFG_MAC_ADDR_SPI_CS 0 56 #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 57 #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3 58 59 #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) 60 61 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH 62 static int get_mac_addr(u8 *addr) 63 { 64 struct spi_flash *flash; 65 int ret; 66 67 flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS, 68 CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE); 69 if (!flash) { 70 printf("Error - unable to probe SPI flash.\n"); 71 return -1; 72 } 73 74 ret = spi_flash_read(flash, CFG_MAC_ADDR_OFFSET, 6, addr); 75 if (ret) { 76 printf("Error - unable to read MAC address from SPI flash.\n"); 77 return -1; 78 } 79 80 return ret; 81 } 82 #endif 83 84 void dsp_lpsc_on(unsigned domain, unsigned int id) 85 { 86 dv_reg_p mdstat, mdctl, ptstat, ptcmd; 87 struct davinci_psc_regs *psc_regs; 88 89 psc_regs = davinci_psc0_regs; 90 mdstat = &psc_regs->psc0.mdstat[id]; 91 mdctl = &psc_regs->psc0.mdctl[id]; 92 ptstat = &psc_regs->ptstat; 93 ptcmd = &psc_regs->ptcmd; 94 95 while (*ptstat & (0x1 << domain)) 96 ; 97 98 if ((*mdstat & 0x1f) == 0x03) 99 return; /* Already on and enabled */ 100 101 *mdctl |= 0x03; 102 103 *ptcmd = 0x1 << domain; 104 105 while (*ptstat & (0x1 << domain)) 106 ; 107 while ((*mdstat & 0x1f) != 0x03) 108 ; /* Probably an overkill... */ 109 } 110 111 static void dspwake(void) 112 { 113 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; 114 u32 val; 115 116 /* if the device is ARM only, return */ 117 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) 118 return; 119 120 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) 121 return; 122 123 *resetvect++ = 0x1E000; /* DSP Idle */ 124 /* clear out the next 10 words as NOP */ 125 memset(resetvect, 0, sizeof(unsigned) *10); 126 127 /* setup the DSP reset vector */ 128 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); 129 130 dsp_lpsc_on(1, DAVINCI_LPSC_GEM); 131 val = readl(PSC0_MDCTL + (15 * 4)); 132 val |= 0x100; 133 writel(val, (PSC0_MDCTL + (15 * 4))); 134 } 135 136 int misc_init_r(void) 137 { 138 dspwake(); 139 140 #if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM) 141 142 uchar env_enetaddr[6]; 143 int enetaddr_found; 144 145 enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr); 146 147 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH 148 int spi_mac_read; 149 uchar buff[6]; 150 151 spi_mac_read = get_mac_addr(buff); 152 153 /* 154 * MAC address not present in the environment 155 * try and read the MAC address from SPI flash 156 * and set it. 157 */ 158 if (!enetaddr_found) { 159 if (!spi_mac_read) { 160 if (is_valid_ether_addr(buff)) { 161 if (eth_setenv_enetaddr("ethaddr", buff)) { 162 printf("Warning: Failed to " 163 "set MAC address from SPI flash\n"); 164 } 165 } else { 166 printf("Warning: Invalid " 167 "MAC address read from SPI flash\n"); 168 } 169 } 170 } else { 171 /* 172 * MAC address present in environment compare it with 173 * the MAC address in SPI flash and warn on mismatch 174 */ 175 if (!spi_mac_read && is_valid_ether_addr(buff) && 176 memcmp(env_enetaddr, buff, 6)) 177 printf("Warning: MAC address in SPI flash don't match " 178 "with the MAC address in the environment\n"); 179 printf("Default using MAC address from environment\n"); 180 } 181 #endif 182 uint8_t enetaddr[8]; 183 int eeprom_mac_read; 184 185 /* Read Ethernet MAC address from EEPROM */ 186 eeprom_mac_read = dvevm_read_mac_address(enetaddr); 187 188 /* 189 * MAC address not present in the environment 190 * try and read the MAC address from EEPROM flash 191 * and set it. 192 */ 193 if (!enetaddr_found) { 194 if (eeprom_mac_read) 195 /* Set Ethernet MAC address from EEPROM */ 196 davinci_sync_env_enetaddr(enetaddr); 197 } else { 198 /* 199 * MAC address present in environment compare it with 200 * the MAC address in EEPROM and warn on mismatch 201 */ 202 if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6)) 203 printf("Warning: MAC address in EEPROM don't match " 204 "with the MAC address in the environment\n"); 205 printf("Default using MAC address from environment\n"); 206 } 207 208 #endif 209 return 0; 210 } 211 212 #ifdef CONFIG_DAVINCI_MMC 213 static struct davinci_mmc mmc_sd0 = { 214 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, 215 .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */ 216 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, 217 .version = MMC_CTLR_VERSION_2, 218 }; 219 220 int board_mmc_init(bd_t *bis) 221 { 222 mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); 223 224 /* Add slot-0 to mmc subsystem */ 225 return davinci_mmc_init(bis, &mmc_sd0); 226 } 227 #endif 228 229 static const struct pinmux_config gpio_pins[] = { 230 #ifdef CONFIG_USE_NOR 231 /* GP0[11] is required for NOR to work on Rev 3 EVMs */ 232 { pinmux(0), 8, 4 }, /* GP0[11] */ 233 #endif 234 #ifdef CONFIG_DAVINCI_MMC 235 /* GP0[11] is required for SD to work on Rev 3 EVMs */ 236 { pinmux(0), 8, 4 }, /* GP0[11] */ 237 #endif 238 }; 239 240 const struct pinmux_resource pinmuxes[] = { 241 #ifdef CONFIG_DRIVER_TI_EMAC 242 PINMUX_ITEM(emac_pins_mdio), 243 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 244 PINMUX_ITEM(emac_pins_rmii), 245 #else 246 PINMUX_ITEM(emac_pins_mii), 247 #endif 248 #endif 249 #ifdef CONFIG_SPI_FLASH 250 PINMUX_ITEM(spi1_pins_base), 251 PINMUX_ITEM(spi1_pins_scs0), 252 #endif 253 PINMUX_ITEM(uart2_pins_txrx), 254 PINMUX_ITEM(uart2_pins_rtscts), 255 PINMUX_ITEM(i2c0_pins), 256 #ifdef CONFIG_NAND_DAVINCI 257 PINMUX_ITEM(emifa_pins_cs3), 258 PINMUX_ITEM(emifa_pins_cs4), 259 PINMUX_ITEM(emifa_pins_nand), 260 #elif defined(CONFIG_USE_NOR) 261 PINMUX_ITEM(emifa_pins_cs2), 262 PINMUX_ITEM(emifa_pins_nor), 263 #endif 264 PINMUX_ITEM(gpio_pins), 265 #ifdef CONFIG_DAVINCI_MMC 266 PINMUX_ITEM(mmc0_pins), 267 #endif 268 }; 269 270 const int pinmuxes_size = ARRAY_SIZE(pinmuxes); 271 272 const struct lpsc_resource lpsc[] = { 273 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ 274 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ 275 { DAVINCI_LPSC_EMAC }, /* image download */ 276 { DAVINCI_LPSC_UART2 }, /* console */ 277 { DAVINCI_LPSC_GPIO }, 278 #ifdef CONFIG_DAVINCI_MMC 279 { DAVINCI_LPSC_MMC_SD }, 280 #endif 281 }; 282 283 const int lpsc_size = ARRAY_SIZE(lpsc); 284 285 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK 286 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 287 #endif 288 289 #define REV_AM18X_EVM 0x100 290 291 /* 292 * get_board_rev() - setup to pass kernel board revision information 293 * Returns: 294 * bit[0-3] Maximum cpu clock rate supported by onboard SoC 295 * 0000b - 300 MHz 296 * 0001b - 372 MHz 297 * 0010b - 408 MHz 298 * 0011b - 456 MHz 299 */ 300 u32 get_board_rev(void) 301 { 302 char *s; 303 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; 304 u32 rev = 0; 305 306 s = getenv("maxcpuclk"); 307 if (s) 308 maxcpuclk = simple_strtoul(s, NULL, 10); 309 310 if (maxcpuclk >= 456000000) 311 rev = 3; 312 else if (maxcpuclk >= 408000000) 313 rev = 2; 314 else if (maxcpuclk >= 372000000) 315 rev = 1; 316 #ifdef CONFIG_DA850_AM18X_EVM 317 rev |= REV_AM18X_EVM; 318 #endif 319 return rev; 320 } 321 322 int board_early_init_f(void) 323 { 324 /* 325 * Power on required peripherals 326 * ARM does not have access by default to PSC0 and PSC1 327 * assuming here that the DSP bootloader has set the IOPU 328 * such that PSC access is available to ARM 329 */ 330 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) 331 return 1; 332 333 return 0; 334 } 335 336 int board_init(void) 337 { 338 #if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC) 339 u32 val; 340 #endif 341 342 #ifndef CONFIG_USE_IRQ 343 irq_init(); 344 #endif 345 346 #ifdef CONFIG_NAND_DAVINCI 347 /* 348 * NAND CS setup - cycle counts based on da850evm NAND timings in the 349 * Linux kernel @ 25MHz EMIFA 350 */ 351 writel((DAVINCI_ABCR_WSETUP(2) | 352 DAVINCI_ABCR_WSTROBE(2) | 353 DAVINCI_ABCR_WHOLD(1) | 354 DAVINCI_ABCR_RSETUP(1) | 355 DAVINCI_ABCR_RSTROBE(4) | 356 DAVINCI_ABCR_RHOLD(0) | 357 DAVINCI_ABCR_TA(1) | 358 DAVINCI_ABCR_ASIZE_8BIT), 359 &davinci_emif_regs->ab2cr); /* CS3 */ 360 #endif 361 362 /* arch number of the board */ 363 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; 364 365 /* address of boot parameters */ 366 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; 367 368 /* setup the SUSPSRC for ARM to control emulation suspend */ 369 writel(readl(&davinci_syscfg_regs->suspsrc) & 370 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | 371 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | 372 DAVINCI_SYSCFG_SUSPSRC_UART2), 373 &davinci_syscfg_regs->suspsrc); 374 375 /* configure pinmux settings */ 376 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) 377 return 1; 378 379 #ifdef CONFIG_USE_NOR 380 /* Set the GPIO direction as output */ 381 clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); 382 383 /* Set the output as low */ 384 val = readl(GPIO_BANK0_REG_SET_ADDR); 385 val |= (0x01 << 11); 386 writel(val, GPIO_BANK0_REG_CLR_ADDR); 387 #endif 388 389 #ifdef CONFIG_DAVINCI_MMC 390 /* Set the GPIO direction as output */ 391 clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); 392 393 /* Set the output as high */ 394 val = readl(GPIO_BANK0_REG_SET_ADDR); 395 val |= (0x01 << 11); 396 writel(val, GPIO_BANK0_REG_SET_ADDR); 397 #endif 398 399 #ifdef CONFIG_DRIVER_TI_EMAC 400 davinci_emac_mii_mode_sel(HAS_RMII); 401 #endif /* CONFIG_DRIVER_TI_EMAC */ 402 403 /* enable the console UART */ 404 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 405 DAVINCI_UART_PWREMU_MGMT_UTRST), 406 &davinci_uart2_ctrl_regs->pwremu_mgmt); 407 408 return 0; 409 } 410 411 #ifdef CONFIG_DRIVER_TI_EMAC 412 413 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 414 /** 415 * rmii_hw_init 416 * 417 * DA850/OMAP-L138 EVM can interface to a daughter card for 418 * additional features. This card has an I2C GPIO Expander TCA6416 419 * to select the required functions like camera, RMII Ethernet, 420 * character LCD, video. 421 * 422 * Initialization of the expander involves configuring the 423 * polarity and direction of the ports. P07-P05 are used here. 424 * These ports are connected to a Mux chip which enables only one 425 * functionality at a time. 426 * 427 * For RMII phy to respond, the MII MDIO clock has to be disabled 428 * since both the PHY devices have address as zero. The MII MDIO 429 * clock is controlled via GPIO2[6]. 430 * 431 * This code is valid for Beta version of the hardware 432 */ 433 int rmii_hw_init(void) 434 { 435 const struct pinmux_config gpio_pins[] = { 436 { pinmux(6), 8, 1 } 437 }; 438 u_int8_t buf[2]; 439 unsigned int temp; 440 int ret; 441 442 /* PinMux for GPIO */ 443 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) 444 return 1; 445 446 /* I2C Exapnder configuration */ 447 /* Set polarity to non-inverted */ 448 buf[0] = 0x0; 449 buf[1] = 0x0; 450 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); 451 if (ret) { 452 printf("\nExpander @ 0x%02x write FAILED!!!\n", 453 CONFIG_SYS_I2C_EXPANDER_ADDR); 454 return ret; 455 } 456 457 /* Configure P07-P05 as outputs */ 458 buf[0] = 0x1f; 459 buf[1] = 0xff; 460 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); 461 if (ret) { 462 printf("\nExpander @ 0x%02x write FAILED!!!\n", 463 CONFIG_SYS_I2C_EXPANDER_ADDR); 464 } 465 466 /* For Ethernet RMII selection 467 * P07(SelA)=0 468 * P06(SelB)=1 469 * P05(SelC)=1 470 */ 471 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 472 printf("\nExpander @ 0x%02x read FAILED!!!\n", 473 CONFIG_SYS_I2C_EXPANDER_ADDR); 474 } 475 476 buf[0] &= 0x1f; 477 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); 478 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 479 printf("\nExpander @ 0x%02x write FAILED!!!\n", 480 CONFIG_SYS_I2C_EXPANDER_ADDR); 481 } 482 483 /* Set the output as high */ 484 temp = REG(GPIO_BANK2_REG_SET_ADDR); 485 temp |= (0x01 << 6); 486 REG(GPIO_BANK2_REG_SET_ADDR) = temp; 487 488 /* Set the GPIO direction as output */ 489 temp = REG(GPIO_BANK2_REG_DIR_ADDR); 490 temp &= ~(0x01 << 6); 491 REG(GPIO_BANK2_REG_DIR_ADDR) = temp; 492 493 return 0; 494 } 495 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ 496 497 /* 498 * Initializes on-board ethernet controllers. 499 */ 500 int board_eth_init(bd_t *bis) 501 { 502 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 503 /* Select RMII fucntion through the expander */ 504 if (rmii_hw_init()) 505 printf("RMII hardware init failed!!!\n"); 506 #endif 507 if (!davinci_emac_initialize()) { 508 printf("Error: Ethernet init failed!\n"); 509 return -1; 510 } 511 512 return 0; 513 } 514 #endif /* CONFIG_DRIVER_TI_EMAC */ 515