1 /* 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Based on da830evm.c. Original Copyrights follow: 5 * 6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 */ 23 24 #include <common.h> 25 #include <i2c.h> 26 #include <net.h> 27 #include <netdev.h> 28 #include <spi.h> 29 #include <spi_flash.h> 30 #include <asm/arch/hardware.h> 31 #include <asm/arch/emif_defs.h> 32 #include <asm/arch/emac_defs.h> 33 #include <asm/arch/pinmux_defs.h> 34 #include <asm/io.h> 35 #include <asm/arch/davinci_misc.h> 36 #include <asm/errno.h> 37 #include <hwconfig.h> 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 #ifdef CONFIG_DRIVER_TI_EMAC 42 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 43 #define HAS_RMII 1 44 #else 45 #define HAS_RMII 0 46 #endif 47 #endif /* CONFIG_DRIVER_TI_EMAC */ 48 49 #define CFG_MAC_ADDR_SPI_BUS 0 50 #define CFG_MAC_ADDR_SPI_CS 0 51 #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 52 #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3 53 54 #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) 55 56 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH 57 static int get_mac_addr(u8 *addr) 58 { 59 struct spi_flash *flash; 60 int ret; 61 62 flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS, 63 CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE); 64 if (!flash) { 65 printf("Error - unable to probe SPI flash.\n"); 66 return -1; 67 } 68 69 ret = spi_flash_read(flash, CFG_MAC_ADDR_OFFSET, 6, addr); 70 if (ret) { 71 printf("Error - unable to read MAC address from SPI flash.\n"); 72 return -1; 73 } 74 75 return ret; 76 } 77 #endif 78 79 void dsp_lpsc_on(unsigned domain, unsigned int id) 80 { 81 dv_reg_p mdstat, mdctl, ptstat, ptcmd; 82 struct davinci_psc_regs *psc_regs; 83 84 psc_regs = davinci_psc0_regs; 85 mdstat = &psc_regs->psc0.mdstat[id]; 86 mdctl = &psc_regs->psc0.mdctl[id]; 87 ptstat = &psc_regs->ptstat; 88 ptcmd = &psc_regs->ptcmd; 89 90 while (*ptstat & (0x1 << domain)) 91 ; 92 93 if ((*mdstat & 0x1f) == 0x03) 94 return; /* Already on and enabled */ 95 96 *mdctl |= 0x03; 97 98 *ptcmd = 0x1 << domain; 99 100 while (*ptstat & (0x1 << domain)) 101 ; 102 while ((*mdstat & 0x1f) != 0x03) 103 ; /* Probably an overkill... */ 104 } 105 106 static void dspwake(void) 107 { 108 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; 109 u32 val; 110 111 /* if the device is ARM only, return */ 112 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) 113 return; 114 115 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) 116 return; 117 118 *resetvect++ = 0x1E000; /* DSP Idle */ 119 /* clear out the next 10 words as NOP */ 120 memset(resetvect, 0, sizeof(unsigned) *10); 121 122 /* setup the DSP reset vector */ 123 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); 124 125 dsp_lpsc_on(1, DAVINCI_LPSC_GEM); 126 val = readl(PSC0_MDCTL + (15 * 4)); 127 val |= 0x100; 128 writel(val, (PSC0_MDCTL + (15 * 4))); 129 } 130 131 int misc_init_r(void) 132 { 133 dspwake(); 134 135 #if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM) 136 137 uchar env_enetaddr[6]; 138 int enetaddr_found; 139 140 enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr); 141 142 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH 143 int spi_mac_read; 144 uchar buff[6]; 145 146 spi_mac_read = get_mac_addr(buff); 147 148 /* 149 * MAC address not present in the environment 150 * try and read the MAC address from SPI flash 151 * and set it. 152 */ 153 if (!enetaddr_found) { 154 if (!spi_mac_read) { 155 if (is_valid_ether_addr(buff)) { 156 if (eth_setenv_enetaddr("ethaddr", buff)) { 157 printf("Warning: Failed to " 158 "set MAC address from SPI flash\n"); 159 } 160 } else { 161 printf("Warning: Invalid " 162 "MAC address read from SPI flash\n"); 163 } 164 } 165 } else { 166 /* 167 * MAC address present in environment compare it with 168 * the MAC address in SPI flash and warn on mismatch 169 */ 170 if (!spi_mac_read && is_valid_ether_addr(buff) && 171 memcmp(env_enetaddr, buff, 6)) 172 printf("Warning: MAC address in SPI flash don't match " 173 "with the MAC address in the environment\n"); 174 printf("Default using MAC address from environment\n"); 175 } 176 #endif 177 uint8_t enetaddr[8]; 178 int eeprom_mac_read; 179 180 /* Read Ethernet MAC address from EEPROM */ 181 eeprom_mac_read = dvevm_read_mac_address(enetaddr); 182 183 /* 184 * MAC address not present in the environment 185 * try and read the MAC address from EEPROM flash 186 * and set it. 187 */ 188 if (!enetaddr_found) { 189 if (eeprom_mac_read) 190 /* Set Ethernet MAC address from EEPROM */ 191 davinci_sync_env_enetaddr(enetaddr); 192 } else { 193 /* 194 * MAC address present in environment compare it with 195 * the MAC address in EEPROM and warn on mismatch 196 */ 197 if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6)) 198 printf("Warning: MAC address in EEPROM don't match " 199 "with the MAC address in the environment\n"); 200 printf("Default using MAC address from environment\n"); 201 } 202 203 #endif 204 return 0; 205 } 206 207 static const struct pinmux_config gpio_pins[] = { 208 #ifdef CONFIG_USE_NOR 209 /* GP0[11] is required for NOR to work on Rev 3 EVMs */ 210 { pinmux(0), 8, 4 }, /* GP0[11] */ 211 #endif 212 }; 213 214 const struct pinmux_resource pinmuxes[] = { 215 #ifdef CONFIG_DRIVER_TI_EMAC 216 PINMUX_ITEM(emac_pins_mdio), 217 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 218 PINMUX_ITEM(emac_pins_rmii), 219 #else 220 PINMUX_ITEM(emac_pins_mii), 221 #endif 222 #endif 223 #ifdef CONFIG_SPI_FLASH 224 PINMUX_ITEM(spi1_pins_base), 225 PINMUX_ITEM(spi1_pins_scs0), 226 #endif 227 PINMUX_ITEM(uart2_pins_txrx), 228 PINMUX_ITEM(uart2_pins_rtscts), 229 PINMUX_ITEM(i2c0_pins), 230 #ifdef CONFIG_NAND_DAVINCI 231 PINMUX_ITEM(emifa_pins_cs3), 232 PINMUX_ITEM(emifa_pins_cs4), 233 PINMUX_ITEM(emifa_pins_nand), 234 #elif defined(CONFIG_USE_NOR) 235 PINMUX_ITEM(emifa_pins_cs2), 236 PINMUX_ITEM(emifa_pins_nor), 237 #endif 238 PINMUX_ITEM(gpio_pins), 239 }; 240 241 const int pinmuxes_size = ARRAY_SIZE(pinmuxes); 242 243 const struct lpsc_resource lpsc[] = { 244 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ 245 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ 246 { DAVINCI_LPSC_EMAC }, /* image download */ 247 { DAVINCI_LPSC_UART2 }, /* console */ 248 { DAVINCI_LPSC_GPIO }, 249 }; 250 251 const int lpsc_size = ARRAY_SIZE(lpsc); 252 253 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK 254 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 255 #endif 256 257 #define REV_AM18X_EVM 0x100 258 259 /* 260 * get_board_rev() - setup to pass kernel board revision information 261 * Returns: 262 * bit[0-3] Maximum cpu clock rate supported by onboard SoC 263 * 0000b - 300 MHz 264 * 0001b - 372 MHz 265 * 0010b - 408 MHz 266 * 0011b - 456 MHz 267 */ 268 u32 get_board_rev(void) 269 { 270 char *s; 271 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; 272 u32 rev = 0; 273 274 s = getenv("maxcpuclk"); 275 if (s) 276 maxcpuclk = simple_strtoul(s, NULL, 10); 277 278 if (maxcpuclk >= 456000000) 279 rev = 3; 280 else if (maxcpuclk >= 408000000) 281 rev = 2; 282 else if (maxcpuclk >= 372000000) 283 rev = 1; 284 #ifdef CONFIG_DA850_AM18X_EVM 285 rev |= REV_AM18X_EVM; 286 #endif 287 return rev; 288 } 289 290 int board_early_init_f(void) 291 { 292 /* 293 * Power on required peripherals 294 * ARM does not have access by default to PSC0 and PSC1 295 * assuming here that the DSP bootloader has set the IOPU 296 * such that PSC access is available to ARM 297 */ 298 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) 299 return 1; 300 301 return 0; 302 } 303 304 int board_init(void) 305 { 306 #ifdef CONFIG_USE_NOR 307 u32 val; 308 #endif 309 310 #ifndef CONFIG_USE_IRQ 311 irq_init(); 312 #endif 313 314 #ifdef CONFIG_NAND_DAVINCI 315 /* 316 * NAND CS setup - cycle counts based on da850evm NAND timings in the 317 * Linux kernel @ 25MHz EMIFA 318 */ 319 writel((DAVINCI_ABCR_WSETUP(0) | 320 DAVINCI_ABCR_WSTROBE(1) | 321 DAVINCI_ABCR_WHOLD(0) | 322 DAVINCI_ABCR_RSETUP(0) | 323 DAVINCI_ABCR_RSTROBE(1) | 324 DAVINCI_ABCR_RHOLD(0) | 325 DAVINCI_ABCR_TA(1) | 326 DAVINCI_ABCR_ASIZE_8BIT), 327 &davinci_emif_regs->ab2cr); /* CS3 */ 328 #endif 329 330 /* arch number of the board */ 331 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; 332 333 /* address of boot parameters */ 334 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; 335 336 /* setup the SUSPSRC for ARM to control emulation suspend */ 337 writel(readl(&davinci_syscfg_regs->suspsrc) & 338 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | 339 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | 340 DAVINCI_SYSCFG_SUSPSRC_UART2), 341 &davinci_syscfg_regs->suspsrc); 342 343 /* configure pinmux settings */ 344 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) 345 return 1; 346 347 #ifdef CONFIG_USE_NOR 348 /* Set the GPIO direction as output */ 349 clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); 350 351 /* Set the output as low */ 352 val = readl(GPIO_BANK0_REG_SET_ADDR); 353 val |= (0x01 << 11); 354 writel(val, GPIO_BANK0_REG_CLR_ADDR); 355 #endif 356 357 #ifdef CONFIG_DRIVER_TI_EMAC 358 davinci_emac_mii_mode_sel(HAS_RMII); 359 #endif /* CONFIG_DRIVER_TI_EMAC */ 360 361 /* enable the console UART */ 362 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | 363 DAVINCI_UART_PWREMU_MGMT_UTRST), 364 &davinci_uart2_ctrl_regs->pwremu_mgmt); 365 366 return 0; 367 } 368 369 #ifdef CONFIG_DRIVER_TI_EMAC 370 371 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 372 /** 373 * rmii_hw_init 374 * 375 * DA850/OMAP-L138 EVM can interface to a daughter card for 376 * additional features. This card has an I2C GPIO Expander TCA6416 377 * to select the required functions like camera, RMII Ethernet, 378 * character LCD, video. 379 * 380 * Initialization of the expander involves configuring the 381 * polarity and direction of the ports. P07-P05 are used here. 382 * These ports are connected to a Mux chip which enables only one 383 * functionality at a time. 384 * 385 * For RMII phy to respond, the MII MDIO clock has to be disabled 386 * since both the PHY devices have address as zero. The MII MDIO 387 * clock is controlled via GPIO2[6]. 388 * 389 * This code is valid for Beta version of the hardware 390 */ 391 int rmii_hw_init(void) 392 { 393 const struct pinmux_config gpio_pins[] = { 394 { pinmux(6), 8, 1 } 395 }; 396 u_int8_t buf[2]; 397 unsigned int temp; 398 int ret; 399 400 /* PinMux for GPIO */ 401 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) 402 return 1; 403 404 /* I2C Exapnder configuration */ 405 /* Set polarity to non-inverted */ 406 buf[0] = 0x0; 407 buf[1] = 0x0; 408 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); 409 if (ret) { 410 printf("\nExpander @ 0x%02x write FAILED!!!\n", 411 CONFIG_SYS_I2C_EXPANDER_ADDR); 412 return ret; 413 } 414 415 /* Configure P07-P05 as outputs */ 416 buf[0] = 0x1f; 417 buf[1] = 0xff; 418 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); 419 if (ret) { 420 printf("\nExpander @ 0x%02x write FAILED!!!\n", 421 CONFIG_SYS_I2C_EXPANDER_ADDR); 422 } 423 424 /* For Ethernet RMII selection 425 * P07(SelA)=0 426 * P06(SelB)=1 427 * P05(SelC)=1 428 */ 429 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 430 printf("\nExpander @ 0x%02x read FAILED!!!\n", 431 CONFIG_SYS_I2C_EXPANDER_ADDR); 432 } 433 434 buf[0] &= 0x1f; 435 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); 436 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { 437 printf("\nExpander @ 0x%02x write FAILED!!!\n", 438 CONFIG_SYS_I2C_EXPANDER_ADDR); 439 } 440 441 /* Set the output as high */ 442 temp = REG(GPIO_BANK2_REG_SET_ADDR); 443 temp |= (0x01 << 6); 444 REG(GPIO_BANK2_REG_SET_ADDR) = temp; 445 446 /* Set the GPIO direction as output */ 447 temp = REG(GPIO_BANK2_REG_DIR_ADDR); 448 temp &= ~(0x01 << 6); 449 REG(GPIO_BANK2_REG_DIR_ADDR) = temp; 450 451 return 0; 452 } 453 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ 454 455 /* 456 * Initializes on-board ethernet controllers. 457 */ 458 int board_eth_init(bd_t *bis) 459 { 460 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII 461 /* Select RMII fucntion through the expander */ 462 if (rmii_hw_init()) 463 printf("RMII hardware init failed!!!\n"); 464 #endif 465 if (!davinci_emac_initialize()) { 466 printf("Error: Ethernet init failed!\n"); 467 return -1; 468 } 469 470 return 0; 471 } 472 #endif /* CONFIG_DRIVER_TI_EMAC */ 473