1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4  *
5  * Based on da830evm.c. Original Copyrights follow:
6  *
7  * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
8  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
9  */
10 
11 #include <common.h>
12 #include <dm.h>
13 #include <environment.h>
14 #include <i2c.h>
15 #include <net.h>
16 #include <netdev.h>
17 #include <spi.h>
18 #include <spi_flash.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/ti-common/davinci_nand.h>
21 #include <asm/arch/emac_defs.h>
22 #include <asm/arch/pinmux_defs.h>
23 #include <asm/io.h>
24 #include <asm/arch/davinci_misc.h>
25 #include <linux/errno.h>
26 #include <hwconfig.h>
27 #include <asm/mach-types.h>
28 #include <asm/gpio.h>
29 
30 #ifdef CONFIG_MMC_DAVINCI
31 #include <mmc.h>
32 #include <asm/arch/sdmmc_defs.h>
33 #endif
34 
35 DECLARE_GLOBAL_DATA_PTR;
36 
37 #ifdef CONFIG_DRIVER_TI_EMAC
38 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
39 #define HAS_RMII 1
40 #else
41 #define HAS_RMII 0
42 #endif
43 #endif /* CONFIG_DRIVER_TI_EMAC */
44 
45 #define CFG_MAC_ADDR_SPI_BUS	0
46 #define CFG_MAC_ADDR_SPI_CS	0
47 #define CFG_MAC_ADDR_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
48 #define CFG_MAC_ADDR_SPI_MODE	SPI_MODE_3
49 
50 #define CFG_MAC_ADDR_OFFSET	(flash->size - SZ_64K)
51 
52 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
53 static int get_mac_addr(u8 *addr)
54 {
55 	struct spi_flash *flash;
56 	int ret;
57 
58 	flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS,
59 			CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE);
60 	if (!flash) {
61 		printf("Error - unable to probe SPI flash.\n");
62 		return -1;
63 	}
64 
65 	ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET) + 1, 7, addr);
66 	if (ret) {
67 		printf("Error - unable to read MAC address from SPI flash.\n");
68 		return -1;
69 	}
70 
71 	return ret;
72 }
73 #endif
74 
75 void dsp_lpsc_on(unsigned domain, unsigned int id)
76 {
77 	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
78 	struct davinci_psc_regs *psc_regs;
79 
80 	psc_regs = davinci_psc0_regs;
81 	mdstat = &psc_regs->psc0.mdstat[id];
82 	mdctl = &psc_regs->psc0.mdctl[id];
83 	ptstat = &psc_regs->ptstat;
84 	ptcmd = &psc_regs->ptcmd;
85 
86 	while (*ptstat & (0x1 << domain))
87 		;
88 
89 	if ((*mdstat & 0x1f) == 0x03)
90 		return;                 /* Already on and enabled */
91 
92 	*mdctl |= 0x03;
93 
94 	*ptcmd = 0x1 << domain;
95 
96 	while (*ptstat & (0x1 << domain))
97 		;
98 	while ((*mdstat & 0x1f) != 0x03)
99 		;		/* Probably an overkill... */
100 }
101 
102 static void dspwake(void)
103 {
104 	unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
105 	u32 val;
106 
107 	/* if the device is ARM only, return */
108 	if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
109 		return;
110 
111 	if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
112 		return;
113 
114 	*resetvect++ = 0x1E000; /* DSP Idle */
115 	/* clear out the next 10 words as NOP */
116 	memset(resetvect, 0, sizeof(unsigned) *10);
117 
118 	/* setup the DSP reset vector */
119 	writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
120 
121 	dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
122 	val = readl(PSC0_MDCTL + (15 * 4));
123 	val |= 0x100;
124 	writel(val, (PSC0_MDCTL + (15 * 4)));
125 }
126 
127 int misc_init_r(void)
128 {
129 	dspwake();
130 
131 #if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM)
132 
133 	uchar env_enetaddr[6];
134 	int enetaddr_found;
135 
136 	enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr);
137 
138 #endif
139 
140 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
141 	int spi_mac_read;
142 	uchar buff[6];
143 
144 	spi_mac_read = get_mac_addr(buff);
145 	buff[0] = 0;
146 
147 	/*
148 	 * MAC address not present in the environment
149 	 * try and read the MAC address from SPI flash
150 	 * and set it.
151 	 */
152 	if (!enetaddr_found) {
153 		if (!spi_mac_read) {
154 			if (is_valid_ethaddr(buff)) {
155 				if (eth_env_set_enetaddr("ethaddr", buff)) {
156 					printf("Warning: Failed to "
157 					"set MAC address from SPI flash\n");
158 				}
159 			} else {
160 					printf("Warning: Invalid "
161 					"MAC address read from SPI flash\n");
162 			}
163 		}
164 	} else {
165 		/*
166 		 * MAC address present in environment compare it with
167 		 * the MAC address in SPI flash and warn on mismatch
168 		 */
169 		if (!spi_mac_read && is_valid_ethaddr(buff) &&
170 		    memcmp(env_enetaddr, buff, 6))
171 			printf("Warning: MAC address in SPI flash don't match "
172 					"with the MAC address in the environment\n");
173 		printf("Default using MAC address from environment\n");
174 	}
175 
176 #elif defined(CONFIG_MAC_ADDR_IN_EEPROM)
177 	uint8_t enetaddr[8];
178 	int eeprom_mac_read;
179 
180 	/* Read Ethernet MAC address from EEPROM */
181 	eeprom_mac_read = dvevm_read_mac_address(enetaddr);
182 
183 	/*
184 	 * MAC address not present in the environment
185 	 * try and read the MAC address from EEPROM flash
186 	 * and set it.
187 	 */
188 	if (!enetaddr_found) {
189 		if (eeprom_mac_read)
190 			/* Set Ethernet MAC address from EEPROM */
191 			davinci_sync_env_enetaddr(enetaddr);
192 	} else {
193 		/*
194 		 * MAC address present in environment compare it with
195 		 * the MAC address in EEPROM and warn on mismatch
196 		 */
197 		if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
198 			printf("Warning: MAC address in EEPROM don't match "
199 					"with the MAC address in the environment\n");
200 		printf("Default using MAC address from environment\n");
201 	}
202 
203 #endif
204 	return 0;
205 }
206 
207 #ifndef CONFIG_DM_MMC
208 #ifdef CONFIG_MMC_DAVINCI
209 static struct davinci_mmc mmc_sd0 = {
210 	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
211 	.host_caps = MMC_MODE_4BIT,     /* DA850 supports only 4-bit SD/MMC */
212 	.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
213 	.version = MMC_CTLR_VERSION_2,
214 };
215 
216 int board_mmc_init(bd_t *bis)
217 {
218 	mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
219 
220 	/* Add slot-0 to mmc subsystem */
221 	return davinci_mmc_init(bis, &mmc_sd0);
222 }
223 #endif
224 #endif
225 
226 static const struct pinmux_config gpio_pins[] = {
227 #ifdef CONFIG_USE_NOR
228 	/* GP0[11] is required for NOR to work on Rev 3 EVMs */
229 	{ pinmux(0), 8, 4 },	/* GP0[11] */
230 #endif
231 #ifdef CONFIG_MMC_DAVINCI
232 	/* GP0[11] is required for SD to work on Rev 3 EVMs */
233 	{ pinmux(0),  8, 4 },	/* GP0[11] */
234 #endif
235 };
236 
237 const struct pinmux_resource pinmuxes[] = {
238 #ifdef CONFIG_DRIVER_TI_EMAC
239 	PINMUX_ITEM(emac_pins_mdio),
240 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
241 	PINMUX_ITEM(emac_pins_rmii),
242 #else
243 	PINMUX_ITEM(emac_pins_mii),
244 #endif
245 #endif
246 #ifdef CONFIG_SPI_FLASH
247 	PINMUX_ITEM(spi1_pins_base),
248 	PINMUX_ITEM(spi1_pins_scs0),
249 #endif
250 	PINMUX_ITEM(uart2_pins_txrx),
251 	PINMUX_ITEM(uart2_pins_rtscts),
252 	PINMUX_ITEM(i2c0_pins),
253 #ifdef CONFIG_NAND_DAVINCI
254 	PINMUX_ITEM(emifa_pins_cs3),
255 	PINMUX_ITEM(emifa_pins_cs4),
256 	PINMUX_ITEM(emifa_pins_nand),
257 #elif defined(CONFIG_USE_NOR)
258 	PINMUX_ITEM(emifa_pins_cs2),
259 	PINMUX_ITEM(emifa_pins_nor),
260 #endif
261 	PINMUX_ITEM(gpio_pins),
262 #ifdef CONFIG_MMC_DAVINCI
263 	PINMUX_ITEM(mmc0_pins),
264 #endif
265 };
266 
267 const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
268 
269 const struct lpsc_resource lpsc[] = {
270 	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
271 	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
272 	{ DAVINCI_LPSC_EMAC },	/* image download */
273 	{ DAVINCI_LPSC_UART2 },	/* console */
274 	{ DAVINCI_LPSC_GPIO },
275 #ifdef CONFIG_MMC_DAVINCI
276 	{ DAVINCI_LPSC_MMC_SD },
277 #endif
278 };
279 
280 const int lpsc_size = ARRAY_SIZE(lpsc);
281 
282 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
283 #define CONFIG_DA850_EVM_MAX_CPU_CLK	300000000
284 #endif
285 
286 #define REV_AM18X_EVM		0x100
287 
288 /*
289  * get_board_rev() - setup to pass kernel board revision information
290  * Returns:
291  * bit[0-3]	Maximum cpu clock rate supported by onboard SoC
292  *		0000b - 300 MHz
293  *		0001b - 372 MHz
294  *		0010b - 408 MHz
295  *		0011b - 456 MHz
296  */
297 u32 get_board_rev(void)
298 {
299 	char *s;
300 	u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
301 	u32 rev = 0;
302 
303 	s = env_get("maxcpuclk");
304 	if (s)
305 		maxcpuclk = simple_strtoul(s, NULL, 10);
306 
307 	if (maxcpuclk >= 456000000)
308 		rev = 3;
309 	else if (maxcpuclk >= 408000000)
310 		rev = 2;
311 	else if (maxcpuclk >= 372000000)
312 		rev = 1;
313 #ifdef CONFIG_DA850_AM18X_EVM
314 	rev |= REV_AM18X_EVM;
315 #endif
316 	return rev;
317 }
318 
319 int board_early_init_f(void)
320 {
321 	/*
322 	 * Power on required peripherals
323 	 * ARM does not have access by default to PSC0 and PSC1
324 	 * assuming here that the DSP bootloader has set the IOPU
325 	 * such that PSC access is available to ARM
326 	 */
327 	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
328 		return 1;
329 
330 	return 0;
331 }
332 
333 int board_init(void)
334 {
335 	irq_init();
336 
337 #ifdef CONFIG_NAND_DAVINCI
338 	/*
339 	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
340 	 * Linux kernel @ 25MHz EMIFA
341 	 */
342 	writel((DAVINCI_ABCR_WSETUP(2) |
343 		DAVINCI_ABCR_WSTROBE(2) |
344 		DAVINCI_ABCR_WHOLD(1) |
345 		DAVINCI_ABCR_RSETUP(1) |
346 		DAVINCI_ABCR_RSTROBE(4) |
347 		DAVINCI_ABCR_RHOLD(0) |
348 		DAVINCI_ABCR_TA(1) |
349 		DAVINCI_ABCR_ASIZE_8BIT),
350 	       &davinci_emif_regs->ab2cr); /* CS3 */
351 #endif
352 
353 	/* arch number of the board */
354 	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
355 
356 	/* address of boot parameters */
357 	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
358 
359 	/* setup the SUSPSRC for ARM to control emulation suspend */
360 	writel(readl(&davinci_syscfg_regs->suspsrc) &
361 	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
362 		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
363 		 DAVINCI_SYSCFG_SUSPSRC_UART2),
364 	       &davinci_syscfg_regs->suspsrc);
365 
366 	/* configure pinmux settings */
367 	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
368 		return 1;
369 
370 #ifdef CONFIG_USE_NOR
371 	/* Set the GPIO direction as output */
372 	clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
373 
374 	/* Set the output as low */
375 	writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
376 #endif
377 
378 #ifdef CONFIG_MMC_DAVINCI
379 	/* Set the GPIO direction as output */
380 	clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
381 
382 	/* Set the output as high */
383 	writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
384 #endif
385 
386 #ifdef CONFIG_DRIVER_TI_EMAC
387 	davinci_emac_mii_mode_sel(HAS_RMII);
388 #endif /* CONFIG_DRIVER_TI_EMAC */
389 
390 	/* enable the console UART */
391 	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
392 		DAVINCI_UART_PWREMU_MGMT_UTRST),
393 	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
394 
395 	return 0;
396 }
397 
398 #ifdef CONFIG_DRIVER_TI_EMAC
399 
400 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
401 /**
402  * rmii_hw_init
403  *
404  * DA850/OMAP-L138 EVM can interface to a daughter card for
405  * additional features. This card has an I2C GPIO Expander TCA6416
406  * to select the required functions like camera, RMII Ethernet,
407  * character LCD, video.
408  *
409  * Initialization of the expander involves configuring the
410  * polarity and direction of the ports. P07-P05 are used here.
411  * These ports are connected to a Mux chip which enables only one
412  * functionality at a time.
413  *
414  * For RMII phy to respond, the MII MDIO clock has to be  disabled
415  * since both the PHY devices have address as zero. The MII MDIO
416  * clock is controlled via GPIO2[6].
417  *
418  * This code is valid for Beta version of the hardware
419  */
420 int rmii_hw_init(void)
421 {
422 	const struct pinmux_config gpio_pins[] = {
423 		{ pinmux(6), 8, 1 }
424 	};
425 	u_int8_t buf[2];
426 	unsigned int temp;
427 	int ret;
428 
429 	/* PinMux for GPIO */
430 	if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
431 		return 1;
432 
433 	/* I2C Exapnder configuration */
434 	/* Set polarity to non-inverted */
435 	buf[0] = 0x0;
436 	buf[1] = 0x0;
437 	ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
438 	if (ret) {
439 		printf("\nExpander @ 0x%02x write FAILED!!!\n",
440 				CONFIG_SYS_I2C_EXPANDER_ADDR);
441 		return ret;
442 	}
443 
444 	/* Configure P07-P05 as outputs */
445 	buf[0] = 0x1f;
446 	buf[1] = 0xff;
447 	ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
448 	if (ret) {
449 		printf("\nExpander @ 0x%02x write FAILED!!!\n",
450 				CONFIG_SYS_I2C_EXPANDER_ADDR);
451 	}
452 
453 	/* For Ethernet RMII selection
454 	 * P07(SelA)=0
455 	 * P06(SelB)=1
456 	 * P05(SelC)=1
457 	 */
458 	if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
459 		printf("\nExpander @ 0x%02x read FAILED!!!\n",
460 				CONFIG_SYS_I2C_EXPANDER_ADDR);
461 	}
462 
463 	buf[0] &= 0x1f;
464 	buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
465 	if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
466 		printf("\nExpander @ 0x%02x write FAILED!!!\n",
467 				CONFIG_SYS_I2C_EXPANDER_ADDR);
468 	}
469 
470 	/* Set the output as high */
471 	temp = REG(GPIO_BANK2_REG_SET_ADDR);
472 	temp |= (0x01 << 6);
473 	REG(GPIO_BANK2_REG_SET_ADDR) = temp;
474 
475 	/* Set the GPIO direction as output */
476 	temp = REG(GPIO_BANK2_REG_DIR_ADDR);
477 	temp &= ~(0x01 << 6);
478 	REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
479 
480 	return 0;
481 }
482 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
483 
484 /*
485  * Initializes on-board ethernet controllers.
486  */
487 int board_eth_init(bd_t *bis)
488 {
489 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
490 	/* Select RMII fucntion through the expander */
491 	if (rmii_hw_init())
492 		printf("RMII hardware init failed!!!\n");
493 #endif
494 	if (!davinci_emac_initialize()) {
495 		printf("Error: Ethernet init failed!\n");
496 		return -1;
497 	}
498 
499 	return 0;
500 }
501 #endif /* CONFIG_DRIVER_TI_EMAC */
502