1*83d290c5STom Rini# SPDX-License-Identifier: GPL-2.0+ 2bfacf466SStefan# 3bfacf466SStefan# Copyright (C) 2011 416437a19SStefan Herbrechtsmeier# Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net> 5bfacf466SStefan# 6bfacf466SStefan# Based on Kirkwood support: 7bfacf466SStefan# (C) Copyright 2009 8bfacf466SStefan# Marvell Semiconductor <www.marvell.com> 9bfacf466SStefan# Written-by: Prafulla Wadaskar <prafulla@marvell.com> 10b1e6c4c3SAnatolij Gustschin# Refer doc/README.kwbimage for more details about how-to configure 11bfacf466SStefan# and create kirkwood boot image 12bfacf466SStefan# 13bfacf466SStefan 14bfacf466SStefan# Boot Media configurations 15bfacf466SStefanBOOT_FROM nand 16bfacf466SStefanNAND_ECC_MODE default 17bfacf466SStefanNAND_PAGE_SIZE 0x0800 18bfacf466SStefan 19bfacf466SStefan# SOC registers configuration using bootrom header extension 20bfacf466SStefan# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 21bfacf466SStefan 22bfacf466SStefan# Configure RGMII-0 interface pad voltage to 1.8V 23bfacf466SStefanDATA 0xFFD100e0 0x1b1b1b9b 24bfacf466SStefan 25bfacf466SStefan#Dram initalization for SINGLE x16 CL=5 @ 400MHz 26bfacf466SStefanDATA 0xFFD01400 0x43000c30 # DDR Configuration register 27bfacf466SStefan# bit13-0: 0xc30, 3120 DDR2 clks refresh rate 28bfacf466SStefan# bit23-14: 0 required 29bfacf466SStefan# bit24: 1, enable exit self refresh mode on DDR access 30bfacf466SStefan# bit25: 1 required 31bfacf466SStefan# bit29-26: 0 required 32bfacf466SStefan# bit31-30: 0b01 required 33bfacf466SStefan 34bfacf466SStefanDATA 0xFFD01404 0x39543000 # DDR Controller Control Low 35bfacf466SStefan# bit3-0: 0 required 36bfacf466SStefan# bit4: 0, addr/cmd in smame cycle 37bfacf466SStefan# bit5: 0, clk is driven during self refresh, we don't care for APX 38bfacf466SStefan# bit6: 0, use recommended falling edge of clk for addr/cmd 39bfacf466SStefan# bit11-7: 0 required 40bfacf466SStefan# bit12: 1 required 41bfacf466SStefan# bit13: 1 required 42bfacf466SStefan# bit14: 0, input buffer always powered up 43bfacf466SStefan# bit17-15: 0 required 44bfacf466SStefan# bit18: 1, cpu lock transaction enabled 45bfacf466SStefan# bit19: 0 required 46bfacf466SStefan# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 47bfacf466SStefan# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 48bfacf466SStefan# bit30-28: 3 required 49bfacf466SStefan# bit31: 0, no additional STARTBURST delay 50bfacf466SStefan 51bfacf466SStefanDATA 0xFFD01408 0x22125451 # DDR Timing (Low) 52bfacf466SStefan# bit3-0: 1, 18 cycle tRAS (tRAS[3-0]) 53bfacf466SStefan# bit7-4: 5, 6 cycle tRCD 54bfacf466SStefan# bit11-8: 4, 5 cyle tRP 55bfacf466SStefan# bit15-12: 5, 6 cyle tWR 56bfacf466SStefan# bit19-16: 2, 3 cyle tWTR 57bfacf466SStefan# bit20: 1, 18 cycle tRAS (tRAS[4]) 58bfacf466SStefan# bit23-21: 0 required 59bfacf466SStefan# bit27-24: 2, 3 cycle tRRD 60bfacf466SStefan# bit31-28: 2, 3 cyle tRTP 61bfacf466SStefan 62bfacf466SStefanDATA 0xFFD0140C 0x00000833 # DDR Timing (High) 63bfacf466SStefan# bit6-0: 0x33, 33 cycle tRFC 64bfacf466SStefan# bit8-7: 0, 1 cycle tR2R 65bfacf466SStefan# bit10-9: 0, 1 cyle tR2W 66bfacf466SStefan# bit12-11: 1, 2 cylce tW2W 67bfacf466SStefan# bit31-13: 0 required 68bfacf466SStefan 69bfacf466SStefanDATA 0xFFD01410 0x0000000c # DDR Address Control 70bfacf466SStefan# bit1-0: 0, Cs0width=x8 71bfacf466SStefan# bit3-2: 3, Cs0size=1Gb 72bfacf466SStefan# bit5-4: 0, Cs1width=nonexistent 73bfacf466SStefan# bit7-6: 0, Cs1size=nonexistent 74bfacf466SStefan# bit9-8: 0, Cs2width=nonexistent 75bfacf466SStefan# bit11-10: 0, Cs2size=nonexistent 76bfacf466SStefan# bit13-12: 0, Cs3width=nonexistent 77bfacf466SStefan# bit15-14: 0, Cs3size=nonexistent 78bfacf466SStefan# bit16: 0, Cs0AddrSel 79bfacf466SStefan# bit17: 0, Cs1AddrSel 80bfacf466SStefan# bit18: 0, Cs2AddrSel 81bfacf466SStefan# bit19: 0, Cs3AddrSel 82bfacf466SStefan# bit31-20: 0 required 83bfacf466SStefan 84bfacf466SStefanDATA 0xFFD01414 0x00000000 # DDR Open Pages Control 85bfacf466SStefan# bit0: 0, OPEn=OpenPage enabled 86bfacf466SStefan# bit31-1: 0 required 87bfacf466SStefan 88bfacf466SStefanDATA 0xFFD01418 0x00000000 # DDR Operation 89bfacf466SStefan# bit3-0: 0, Cmd=Normal SDRAM Mode 90bfacf466SStefan# bit31-4: 0 required 91bfacf466SStefan 92bfacf466SStefanDATA 0xFFD0141C 0x00000C52 # DDR Mode 93bfacf466SStefan# bit2-0: 2, Burst Length (2 required) 94bfacf466SStefan# bit3: 0, Burst Type (0 required) 95bfacf466SStefan# bit6-4: 5, CAS Latency (CL) 5 96bfacf466SStefan# bit7: 0, (Test Mode) Normal operation 97bfacf466SStefan# bit8: 0, (Reset DLL) Normal operation 98bfacf466SStefan# bit11-9: 0, Write recovery for auto-precharge (3 required ??) 99bfacf466SStefan# bit12: 0, Fast Active power down exit time (0 required) 100bfacf466SStefan# bit31-13: 0 required 101bfacf466SStefan 102bfacf466SStefanDATA 0xFFD01420 0x00000040 # DDR Extended Mode 103bfacf466SStefan# bit0: 0, DRAM DLL enabled 104bfacf466SStefan# bit1: 0, DRAM drive strength normal 105bfacf466SStefan# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination) 106bfacf466SStefan# bit5-3: 0 required 107bfacf466SStefan# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination) 108bfacf466SStefan# bit9-7: 0 required 109bfacf466SStefan# bit10: 0, differential DQS enabled 110bfacf466SStefan# bit11: 0 required 111bfacf466SStefan# bit12: 0, DRAM output buffer enabled 112bfacf466SStefan# bit31-13: 0 required 113bfacf466SStefan 114bfacf466SStefanDATA 0xFFD01424 0x0000F17F # DDR Controller Control High 115bfacf466SStefan# bit2-0: 0x7 required 116bfacf466SStefan# bit3: 1, MBUS Burst Chop disabled 117bfacf466SStefan# bit6-4: 0x7 required 118bfacf466SStefan# bit7: 0 required 119bfacf466SStefan# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz 120bfacf466SStefan# bit9: 0, no half clock cycle addition to dataout 121bfacf466SStefan# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals 122bfacf466SStefan# bit11: 0, 1/4 clock cycle skew disabled for write mesh 123bfacf466SStefan# bit15-12: 0xf required 124bfacf466SStefan# bit31-16: 0 required 125bfacf466SStefan 126bfacf466SStefanDATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing 127bfacf466SStefan# bit3-0: 0 required 128bfacf466SStefan# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal 129bfacf466SStefan# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal 130bfacf466SStefan# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal 131bfacf466SStefan# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 132bfacf466SStefan# bit31-20: 0 required 133bfacf466SStefan 134bfacf466SStefanDATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing 135bfacf466SStefan# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal 136bfacf466SStefan# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal 137bfacf466SStefan# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal 138bfacf466SStefan# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 139bfacf466SStefan# bit31-16: 0 required 140bfacf466SStefan 141bfacf466SStefanDATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 142bfacf466SStefanDATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size 143bfacf466SStefan# bit0: 1, Window enabled 144bfacf466SStefan# bit1: 0, Write Protect disabled 145bfacf466SStefan# bit3-2: 0x0, CS0 hit selected 146bfacf466SStefan# bit23-4: 0xfffff required 147bfacf466SStefan# bit31-24: 0x0f, Size (i.e. 256MB) 148bfacf466SStefan 149bfacf466SStefanDATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb 150bfacf466SStefanDATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 151bfacf466SStefan# bit0: 1, Window enabled 152bfacf466SStefan# bit1: 0, Write Protect disabled 153bfacf466SStefan# bit3-2: 1, CS1 hit selected 154bfacf466SStefan# bit23-4: 0xfffff required 155bfacf466SStefan# bit31-24: 0x0f, Size (i.e. 256MB) 156bfacf466SStefan 157bfacf466SStefanDATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled 158bfacf466SStefanDATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled 159bfacf466SStefan 160bfacf466SStefanDATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) 161bfacf466SStefan# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM 162bfacf466SStefan# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM 163bfacf466SStefan# bit15-8: 0 required 164bfacf466SStefan# bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1 165bfacf466SStefan# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM 166bfacf466SStefan# bit31-24: 0 required 167bfacf466SStefan 168bfacf466SStefanDATA 0xFFD01498 0x00000000 # DDR ODT Control (High) 169bfacf466SStefan# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register 170bfacf466SStefan# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register 171bfacf466SStefan# bit31-4 0 required 172bfacf466SStefan 173bfacf466SStefanDATA 0xFFD0149C 0x0000E803 # CPU ODT Control 174bfacf466SStefan# bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1 175bfacf466SStefan# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4 176bfacf466SStefan# bit9-8: 0, Internal ODT assertion is controlled by fiels 177bfacf466SStefan# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm 178bfacf466SStefan# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm 179bfacf466SStefan# bit14: 1, M_STARTBURST_IN ODT enabled 180bfacf466SStefan# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values 181bfacf466SStefan# bit20-16: 0, Pad N channel driving strength for ODT 182bfacf466SStefan# bit25-21: 0, Pad P channel driving strength for ODT 183bfacf466SStefan# bit31-26: 0 required 184bfacf466SStefan 185bfacf466SStefanDATA 0xFFD01480 0x00000001 # DDR Initialization Control 186bfacf466SStefan# bit0: 1, enable DDR init upon this register write 187bfacf466SStefan# bit31-1: 0, required 188bfacf466SStefan 189bfacf466SStefan# End of Header extension 190bfacf466SStefanDATA 0x0 0x0 191