1 /* 2 * Copyright (C) 2011 3 * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net> 4 * 5 * Based on Kirkwood support: 6 * (C) Copyright 2009 7 * Marvell Semiconductor <www.marvell.com> 8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <miiphy.h> 15 #include <netdev.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/soc.h> 18 #include <asm/arch/mpp.h> 19 #include <asm/arch/gpio.h> 20 #include "dns325.h" 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 int board_early_init_f(void) 25 { 26 /* Gpio configuration */ 27 mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH, 28 DNS325_OE_LOW, DNS325_OE_HIGH); 29 30 /* Multi-Purpose Pins Functionality configuration */ 31 static const u32 kwmpp_config[] = { 32 MPP0_NF_IO2, 33 MPP1_NF_IO3, 34 MPP2_NF_IO4, 35 MPP3_NF_IO5, 36 MPP4_NF_IO6, 37 MPP5_NF_IO7, 38 MPP6_SYSRST_OUTn, 39 MPP7_GPO, 40 MPP8_TW_SDA, 41 MPP9_TW_SCK, 42 MPP10_UART0_TXD, 43 MPP11_UART0_RXD, 44 MPP12_SD_CLK, 45 MPP13_SD_CMD, 46 MPP14_SD_D0, 47 MPP15_SD_D1, 48 MPP16_SD_D2, 49 MPP17_SD_D3, 50 MPP18_NF_IO0, 51 MPP19_NF_IO1, 52 MPP20_SATA1_ACTn, /* sata1(left) status led */ 53 MPP21_SATA0_ACTn, /* sata0(right) status led */ 54 MPP22_GPIO, 55 MPP23_GPIO, 56 MPP24_GPIO, /* power off out */ 57 MPP25_GPIO, 58 MPP26_GPIO, /* power led */ 59 MPP27_GPIO, /* sata0(right) error led */ 60 MPP28_GPIO, /* sata1(left) error led */ 61 MPP29_GPIO, /* usb error led */ 62 MPP30_GPIO, 63 MPP31_GPIO, 64 MPP32_GPIO, 65 MPP33_GPIO, 66 MPP34_GPIO, /* power key */ 67 MPP35_GPIO, 68 MPP36_GPIO, 69 MPP37_GPIO, 70 MPP38_GPIO, 71 MPP39_GPIO, /* enable sata 0 */ 72 MPP40_GPIO, /* enable sata 1 */ 73 MPP41_GPIO, /* hdd0 present */ 74 MPP42_GPIO, /* hdd1 present */ 75 MPP43_GPIO, /* usb status led */ 76 MPP44_GPIO, /* fan status */ 77 MPP45_GPIO, /* fan high speed */ 78 MPP46_GPIO, /* fan low speed */ 79 MPP47_GPIO, /* usb umount */ 80 MPP48_GPIO, /* factory reset */ 81 MPP49_GPIO, /* thermal sensor */ 82 0 83 }; 84 kirkwood_mpp_conf(kwmpp_config, NULL); 85 86 kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1); 87 88 kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1); 89 return 0; 90 } 91 92 int board_init(void) 93 { 94 /* Boot parameters address */ 95 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 96 97 return 0; 98 } 99 100 #ifdef CONFIG_RESET_PHY_R 101 /* Configure and initialize PHY */ 102 void reset_phy(void) 103 { 104 u16 reg; 105 u16 devadr; 106 char *name = "egiga0"; 107 108 if (miiphy_set_current_dev(name)) 109 return; 110 111 /* command to read PHY dev address */ 112 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { 113 printf("Err..(%s) could not read PHY dev address\n", __func__); 114 return; 115 } 116 117 /* 118 * Enable RGMII delay on Tx and Rx for CPU port 119 * Ref: sec 4.7.2 of chip datasheet 120 */ 121 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 122 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); 123 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 124 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); 125 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 126 127 /* reset the phy */ 128 miiphy_reset(name, devadr); 129 130 debug("88E1116 Initialized on %s\n", name); 131 } 132 #endif /* CONFIG_RESET_PHY_R */ 133