1 /* 2 * Copyright (C) 2010-2017 CS Systemes d'Information 3 * Florent Trinh Thai <florent.trinh-thai@c-s.fr> 4 * Christophe Leroy <christophe.leroy@c-s.fr> 5 * 6 * Board specific routines for the MCR3000 board 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <hwconfig.h> 13 #include <mpc8xx.h> 14 #include <fdt_support.h> 15 #include <asm/io.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #define SDRAM_MAX_SIZE (32 * 1024 * 1024) 20 21 static const uint cs1_dram_table_66[] = { 22 /* DRAM - single read. (offset 0 in upm RAM) */ 23 0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400, 24 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 25 26 /* DRAM - burst read. (offset 8 in upm RAM) */ 27 0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00, 28 0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05, 29 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 30 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 31 32 /* DRAM - single write. (offset 18 in upm RAM) */ 33 0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804, 34 0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 35 36 /* DRAM - burst write. (offset 20 in upm RAM) */ 37 0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00, 38 0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404, 39 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 40 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 41 42 /* refresh (offset 30 in upm RAM) */ 43 0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04, 44 0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF, 45 46 /* init */ 47 0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF, 48 49 /* exception. (offset 3c in upm RAM) */ 50 0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 51 }; 52 53 int ft_board_setup(void *blob, bd_t *bd) 54 { 55 const char *sync = "receive"; 56 57 ft_cpu_setup(blob, bd); 58 59 /* BRG */ 60 do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency", 61 bd->bi_busfreq, 1); 62 63 /* MAC addr */ 64 fdt_fixup_ethernet(blob); 65 66 /* Bus Frequency for CPM */ 67 do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1); 68 69 /* E1 interface - Set data rate */ 70 do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1); 71 72 /* E1 interface - Set channel phase to 0 */ 73 do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1); 74 75 /* E1 interface - rising edge sync pulse transmit */ 76 do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse", 77 sync, strlen(sync), 1); 78 79 return 0; 80 } 81 82 int checkboard(void) 83 { 84 serial_puts("BOARD: MCR3000 CSSI\n"); 85 86 return 0; 87 } 88 89 int dram_init(void) 90 { 91 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; 92 memctl8xx_t __iomem *memctl = &immap->im_memctl; 93 94 printf("UPMA init for SDRAM (CAS latency 2), "); 95 printf("init address 0x%08x, size ", (int)dram_init); 96 /* Configure UPMA for cs1 */ 97 upmconfig(UPMA, (uint *)cs1_dram_table_66, 98 sizeof(cs1_dram_table_66) / sizeof(uint)); 99 udelay(10); 100 out_be16(&memctl->memc_mptpr, 0x0200); 101 out_be32(&memctl->memc_mamr, 0x14904000); 102 udelay(10); 103 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM); 104 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM); 105 udelay(10); 106 out_be32(&memctl->memc_mcr, 0x80002830); 107 out_be32(&memctl->memc_mar, 0x00000088); 108 out_be32(&memctl->memc_mcr, 0x80002038); 109 udelay(200); 110 111 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 112 SDRAM_MAX_SIZE); 113 114 return 0; 115 } 116 117 int misc_init_r(void) 118 { 119 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; 120 iop8xx_t __iomem *iop = &immr->im_ioport; 121 122 /* Set port C13 as GPIO (BTN_ACQ_AL) */ 123 clrbits_be16(&iop->iop_pcpar, 0x4); 124 clrbits_be16(&iop->iop_pcdir, 0x4); 125 126 /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */ 127 if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0) 128 env_set("bootdelay", "60"); 129 130 return 0; 131 } 132 133 int board_early_init_f(void) 134 { 135 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; 136 137 /* 138 * Erase FPGA(s) for reboot 139 */ 140 clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */ 141 setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */ 142 udelay(1); /* Wait more than 300ns */ 143 setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */ 144 145 return 0; 146 } 147