1 /*
2  * (C) Copyright 2012
3  * Corscience GmbH & Co. KG, <www.corscience.de>
4  * Thomas Weber <weber@corscience.de>
5  * Sunil Kumar <sunilsaini05@gmail.com>
6  * Shashi Ranjan <shashiranjanmca05@gmail.com>
7  *
8  * Derived from Devkit8000 code by
9  * Frederik Kriewitz <frederik@kriewitz.eu>
10  *
11  * SPDX-License-Identifier:	GPL-2.0+
12  */
13 #include <common.h>
14 #include <twl4030.h>
15 #include <asm/io.h>
16 #include <asm/arch/mmc_host_def.h>
17 #include <asm/arch/mux.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/arch/mem.h>
20 #include "tricorder.h"
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 
24 /*
25  * Routine: board_init
26  * Description: Early hardware init.
27  */
28 int board_init(void)
29 {
30 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
31 	/* boot param addr */
32 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
33 
34 	return 0;
35 }
36 
37 /*
38  * Routine: misc_init_r
39  * Description: Configure board specific parts
40  */
41 int misc_init_r(void)
42 {
43 	twl4030_power_init();
44 #ifdef CONFIG_TWL4030_LED
45 	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
46 #endif
47 
48 	dieid_num_r();
49 
50 	return 0;
51 }
52 
53 /*
54  * Routine: set_muxconf_regs
55  * Description: Setting up the configuration Mux registers specific to the
56  *		hardware. Many pins need to be moved from protect to primary
57  *		mode.
58  */
59 void set_muxconf_regs(void)
60 {
61 	MUX_TRICORDER();
62 }
63 
64 #if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD))
65 int board_mmc_init(bd_t *bis)
66 {
67 	return omap_mmc_init(0, 0, 0, -1, -1);
68 }
69 #endif
70 
71 /*
72  * Routine: get_board_mem_timings
73  * Description: If we use SPL then there is no x-loader nor config header
74  * so we have to setup the DDR timings ourself on the first bank.  This
75  * provides the timing values back to the function that configures
76  * the memory.  We have either one or two banks of 128MB DDR.
77  */
78 void get_board_mem_timings(struct board_sdrc_timings *timings)
79 {
80 	/* General SDRC config */
81 	timings->mcfg = MICRON_V_MCFG_165(128 << 20);
82 	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
83 
84 	/* AC timings */
85 	timings->ctrla = MICRON_V_ACTIMA_165;
86 	timings->ctrlb = MICRON_V_ACTIMB_165;
87 	timings->mr = MICRON_V_MR_165;
88 }
89