1 /*
2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3  * Based on mx6qsabrelite.c file
4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
5  * Leo Sartre, <lsartre@adeneo-embedded.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #include <common.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/gpio.h>
17 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/boot_mode.h>
19 #include <mmc.h>
20 #include <fsl_esdhc.h>
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 
24 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
25 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
26 
27 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
28 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
29 
30 int dram_init(void)
31 {
32 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
33 
34 	return 0;
35 }
36 
37 iomux_v3_cfg_t const uart2_pads[] = {
38 	MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
39 	MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
40 };
41 
42 iomux_v3_cfg_t const usdhc2_pads[] = {
43 	MX6_PAD_SD2_CLK__USDHC2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
44 	MX6_PAD_SD2_CMD__USDHC2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
45 	MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
46 	MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
47 	MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
48 	MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
49 	MX6_PAD_GPIO_4__GPIO_1_4      | MUX_PAD_CTRL(USDHC_PAD_CTRL),
50 };
51 
52 iomux_v3_cfg_t const usdhc4_pads[] = {
53 	MX6_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
54 	MX6_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
55 	MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
56 	MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 	MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 	MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 	MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 	MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
61 	MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
62 	MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
63 	MX6_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
64 };
65 
66 static void setup_iomux_uart(void)
67 {
68 	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
69 }
70 
71 #ifdef CONFIG_FSL_ESDHC
72 struct fsl_esdhc_cfg usdhc_cfg[] = {
73 	{USDHC2_BASE_ADDR},
74 	{USDHC4_BASE_ADDR},
75 };
76 
77 int board_mmc_getcd(struct mmc *mmc)
78 {
79 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
80 	int ret = 0;
81 
82 	switch (cfg->esdhc_base) {
83 	case USDHC2_BASE_ADDR:
84 		gpio_direction_input(IMX_GPIO_NR(1, 4));
85 		ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
86 		break;
87 	case USDHC4_BASE_ADDR:
88 		gpio_direction_input(IMX_GPIO_NR(2, 6));
89 		ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
90 		break;
91 	default:
92 		printf("Bad USDHC interface\n");
93 	}
94 
95 	return ret;
96 }
97 
98 int board_mmc_init(bd_t *bis)
99 {
100 	s32 status = 0;
101 
102 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
103 	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
104 
105 	imx_iomux_v3_setup_multiple_pads(
106 				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
107 	imx_iomux_v3_setup_multiple_pads(
108 				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
109 
110 	status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
111 		     fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
112 
113 	return status;
114 }
115 #endif
116 
117 int board_early_init_f(void)
118 {
119 	setup_iomux_uart();
120 
121 	return 0;
122 }
123 
124 int board_init(void)
125 {
126 	/* address of boot parameters */
127 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
128 
129 	return 0;
130 }
131 
132 int checkboard(void)
133 {
134 	puts("Board: Conga-QEVAL QMX6 Quad\n");
135 
136 	return 0;
137 }
138 
139 #ifdef CONFIG_CMD_BMODE
140 static const struct boot_mode board_boot_modes[] = {
141 	/* 4 bit bus width */
142 	{"mmc0",	MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
143 	{"mmc1",	MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
144 	{NULL,		0},
145 };
146 #endif
147 
148 int misc_init_r(void)
149 {
150 #ifdef CONFIG_CMD_BMODE
151 	add_board_boot_modes(board_boot_modes);
152 #endif
153 	return 0;
154 }
155