1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 Compulab, Ltd. 4 */ 5 6 #include <common.h> 7 #include <spl.h> 8 #include <i2c.h> 9 #include <asm/arch/clock.h> 10 #include <asm/arch/ddr_defs.h> 11 #include <asm/gpio.h> 12 #include <power/pmic.h> 13 #include <power/tps65218.h> 14 #include "board.h" 15 16 const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 }; 17 const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 }; 18 const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 }; 19 const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 }; 20 21 const struct ctrl_ioregs ioregs_ddr3 = { 22 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, 23 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, 24 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, 25 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, 26 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, 27 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, 28 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, 29 .emif_sdram_config_ext = 0x0143, 30 }; 31 32 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ 33 struct emif_regs ddr3_emif_regs = { 34 .sdram_config = 0x638413B2, 35 .ref_ctrl = 0x00000C30, 36 .sdram_tim1 = 0xEAAAD4DB, 37 .sdram_tim2 = 0x266B7FDA, 38 .sdram_tim3 = 0x107F8678, 39 .read_idle_ctrl = 0x00050000, 40 .zq_config = 0x50074BE4, 41 .temp_alert_config = 0x0, 42 .emif_ddr_phy_ctlr_1 = 0x0E004008, 43 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 44 .emif_ddr_ext_phy_ctrl_2 = 0x00000066, 45 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 46 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, 47 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, 48 .emif_rd_wr_exec_thresh = 0x80000405, 49 .emif_prio_class_serv_map = 0x80000001, 50 .emif_connect_id_serv_1_map = 0x80000094, 51 .emif_connect_id_serv_2_map = 0x00000000, 52 .emif_cos_config = 0x000FFFFF 53 }; 54 55 const u32 ext_phy_ctrl_const_base_ddr3[] = { 56 0x00000000, 57 0x00000044, 58 0x00000044, 59 0x00000046, 60 0x00000046, 61 0x00000000, 62 0x00000059, 63 0x00000077, 64 0x00000093, 65 0x000000A8, 66 0x00000000, 67 0x00000019, 68 0x00000037, 69 0x00000053, 70 0x00000068, 71 0x00000000, 72 0x0, 73 0x0, 74 0x40000000, 75 0x08102040 76 }; 77 78 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) 79 { 80 *regs = ext_phy_ctrl_const_base_ddr3; 81 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); 82 } 83 84 const struct dpll_params *get_dpll_ddr_params(void) 85 { 86 return &dpll_ddr; 87 } 88 89 const struct dpll_params *get_dpll_mpu_params(void) 90 { 91 return &dpll_mpu; 92 } 93 94 const struct dpll_params *get_dpll_core_params(void) 95 { 96 return &dpll_core; 97 } 98 99 const struct dpll_params *get_dpll_per_params(void) 100 { 101 return &dpll_per; 102 } 103 104 void scale_vcores(void) 105 { 106 set_i2c_pin_mux(); 107 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 108 if (i2c_probe(TPS65218_CHIP_PM)) 109 return; 110 111 tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV); 112 tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV); 113 } 114 115 void sdram_init(void) 116 { 117 unsigned long ram_size; 118 119 config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); 120 ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); 121 if (ram_size == 0x80000000 || 122 ram_size == 0x40000000 || 123 ram_size == 0x20000000) 124 return; 125 126 ddr3_emif_regs.sdram_config = 0x638453B2; 127 config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); 128 ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); 129 if (ram_size == 0x08000000) 130 return; 131 132 hang(); 133 } 134 135