1*b09bf723SIgor Grinberg /* 2*b09bf723SIgor Grinberg * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> 3*b09bf723SIgor Grinberg * 4*b09bf723SIgor Grinberg * Authors: Igor Grinberg <grinberg@compulab.co.il> 5*b09bf723SIgor Grinberg * 6*b09bf723SIgor Grinberg * SPDX-License-Identifier: GPL-2.0+ 7*b09bf723SIgor Grinberg */ 8*b09bf723SIgor Grinberg 9*b09bf723SIgor Grinberg #include <common.h> 10*b09bf723SIgor Grinberg #include <asm/arch/sys_proto.h> 11*b09bf723SIgor Grinberg #include <asm/arch/mux.h> 12*b09bf723SIgor Grinberg #include <asm/io.h> 13*b09bf723SIgor Grinberg 14*b09bf723SIgor Grinberg void set_muxconf_regs(void) 15*b09bf723SIgor Grinberg { 16*b09bf723SIgor Grinberg /* SDRC */ 17*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); 18*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); 19*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); 20*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); 21*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); 22*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); 23*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); 24*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); 25*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); 26*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); 27*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); 28*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); 29*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); 30*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); 31*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); 32*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); 33*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); 34*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); 35*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); 36*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); 37*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); 38*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); 39*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); 40*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); 41*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); 42*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); 43*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); 44*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); 45*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); 46*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); 47*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); 48*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); 49*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); 50*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); 51*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); 52*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); 53*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); 54*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); 55*b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); 56*b09bf723SIgor Grinberg 57*b09bf723SIgor Grinberg /* GPMC */ 58*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); 59*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); 60*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); 61*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); 62*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); 63*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); 64*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); 65*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); 66*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); 67*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); 68*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); 69*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); 70*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); 71*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); 72*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); 73*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); 74*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); 75*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); 76*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); 77*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); 78*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); 79*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); 80*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); 81*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); 82*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); 83*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); 84*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); 85*b09bf723SIgor Grinberg 86*b09bf723SIgor Grinberg /* SB-T35 SD/MMC WP GPIO59 */ 87*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/ 88*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); 89*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); 90*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); 91*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); 92*b09bf723SIgor Grinberg /* SB-T35 Audio Enable GPIO61 */ 93*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/ 94*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); 95*b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); 96*b09bf723SIgor Grinberg 97*b09bf723SIgor Grinberg /* UART3 Console */ 98*b09bf723SIgor Grinberg MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); 99*b09bf723SIgor Grinberg MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); 100*b09bf723SIgor Grinberg /* RTC V3020 nCS GPIO163 */ 101*b09bf723SIgor Grinberg MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/ 102*b09bf723SIgor Grinberg 103*b09bf723SIgor Grinberg /* SB-T35 SD/MMC CD GPIO144 */ 104*b09bf723SIgor Grinberg MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/ 105*b09bf723SIgor Grinberg /* WIFI nRESET GPIO145 */ 106*b09bf723SIgor Grinberg MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/ 107*b09bf723SIgor Grinberg 108*b09bf723SIgor Grinberg /* MMC1 */ 109*b09bf723SIgor Grinberg MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); 110*b09bf723SIgor Grinberg MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); 111*b09bf723SIgor Grinberg MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); 112*b09bf723SIgor Grinberg MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); 113*b09bf723SIgor Grinberg MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); 114*b09bf723SIgor Grinberg MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); 115*b09bf723SIgor Grinberg 116*b09bf723SIgor Grinberg /* I2C */ 117*b09bf723SIgor Grinberg MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); 118*b09bf723SIgor Grinberg MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); 119*b09bf723SIgor Grinberg MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); 120*b09bf723SIgor Grinberg MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); 121*b09bf723SIgor Grinberg 122*b09bf723SIgor Grinberg /* Green LED GPIO186 */ 123*b09bf723SIgor Grinberg MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/ 124*b09bf723SIgor Grinberg 125*b09bf723SIgor Grinberg /* RTC V3020 CS Enable GPIO160 */ 126*b09bf723SIgor Grinberg MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/ 127*b09bf723SIgor Grinberg 128*b09bf723SIgor Grinberg /* SYS_BOOT */ 129*b09bf723SIgor Grinberg MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/ 130*b09bf723SIgor Grinberg MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/ 131*b09bf723SIgor Grinberg MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/ 132*b09bf723SIgor Grinberg MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/ 133*b09bf723SIgor Grinberg MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/ 134*b09bf723SIgor Grinberg MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/ 135*b09bf723SIgor Grinberg } 136