1b09bf723SIgor Grinberg /* 2b09bf723SIgor Grinberg * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> 3b09bf723SIgor Grinberg * 4b09bf723SIgor Grinberg * Authors: Igor Grinberg <grinberg@compulab.co.il> 5b09bf723SIgor Grinberg * 6b09bf723SIgor Grinberg * SPDX-License-Identifier: GPL-2.0+ 7b09bf723SIgor Grinberg */ 8b09bf723SIgor Grinberg 9b09bf723SIgor Grinberg #include <common.h> 10b09bf723SIgor Grinberg #include <asm/arch/sys_proto.h> 11b09bf723SIgor Grinberg #include <asm/arch/mux.h> 12b09bf723SIgor Grinberg #include <asm/io.h> 13b09bf723SIgor Grinberg 14b09bf723SIgor Grinberg void set_muxconf_regs(void) 15b09bf723SIgor Grinberg { 16b09bf723SIgor Grinberg /* SDRC */ 17b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); 18b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); 19b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); 20b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); 21b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); 22b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); 23b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); 24b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); 25b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); 26b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); 27b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); 28b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); 29b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); 30b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); 31b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); 32b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); 33b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); 34b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); 35b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); 36b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); 37b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); 38b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); 39b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); 40b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); 41b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); 42b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); 43b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); 44b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); 45b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); 46b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); 47b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); 48b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); 49b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); 50b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); 51b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); 52b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); 53b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); 54b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); 55b09bf723SIgor Grinberg MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); 56b09bf723SIgor Grinberg 57b09bf723SIgor Grinberg /* GPMC */ 58b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); 59b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); 60b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); 61b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); 62b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); 63b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); 64b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); 65b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); 66b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); 67b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); 68b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); 69b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); 70b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); 71b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); 72b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); 73b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); 74b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); 75b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); 76b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); 77b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); 78b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); 79b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); 80b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); 81b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); 82b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); 83b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); 84b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); 85b09bf723SIgor Grinberg 86b09bf723SIgor Grinberg /* SB-T35 SD/MMC WP GPIO59 */ 87b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/ 88b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); 89b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); 90b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); 91b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); 92b09bf723SIgor Grinberg /* SB-T35 Audio Enable GPIO61 */ 93b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/ 94b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); 95b09bf723SIgor Grinberg MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); 96b09bf723SIgor Grinberg 97b09bf723SIgor Grinberg /* UART3 Console */ 98b09bf723SIgor Grinberg MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); 99b09bf723SIgor Grinberg MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); 100b09bf723SIgor Grinberg /* RTC V3020 nCS GPIO163 */ 101b09bf723SIgor Grinberg MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/ 102b09bf723SIgor Grinberg 103b09bf723SIgor Grinberg /* SB-T35 SD/MMC CD GPIO144 */ 104b09bf723SIgor Grinberg MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/ 105b09bf723SIgor Grinberg /* WIFI nRESET GPIO145 */ 106b09bf723SIgor Grinberg MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/ 107*011f5c13SIgor Grinberg /* USB1 PHY Reset GPIO 146 */ 108*011f5c13SIgor Grinberg MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/ 109*011f5c13SIgor Grinberg /* USB2 PHY Reset GPIO 147 */ 110*011f5c13SIgor Grinberg MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/ 111b09bf723SIgor Grinberg 112b09bf723SIgor Grinberg /* MMC1 */ 113b09bf723SIgor Grinberg MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); 114b09bf723SIgor Grinberg MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); 115b09bf723SIgor Grinberg MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); 116b09bf723SIgor Grinberg MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); 117b09bf723SIgor Grinberg MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); 118b09bf723SIgor Grinberg MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); 119b09bf723SIgor Grinberg 120b09bf723SIgor Grinberg /* I2C */ 121b09bf723SIgor Grinberg MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); 122b09bf723SIgor Grinberg MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); 123b09bf723SIgor Grinberg MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); 124b09bf723SIgor Grinberg MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); 125b09bf723SIgor Grinberg 126*011f5c13SIgor Grinberg /* SB-T35 USB HUB Reset GPIO98 */ 127*011f5c13SIgor Grinberg MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/ 128*011f5c13SIgor Grinberg /* CM-T3517 USB HUB Reset GPIO152 */ 129*011f5c13SIgor Grinberg MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ 130*011f5c13SIgor Grinberg 131b09bf723SIgor Grinberg /* Green LED GPIO186 */ 132b09bf723SIgor Grinberg MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/ 133b09bf723SIgor Grinberg 134b09bf723SIgor Grinberg /* RTC V3020 CS Enable GPIO160 */ 135b09bf723SIgor Grinberg MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/ 136b09bf723SIgor Grinberg 137*011f5c13SIgor Grinberg /* USB0 - mUSB */ 138*011f5c13SIgor Grinberg MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)); 139*011f5c13SIgor Grinberg /* USB1 EHCI */ 140*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ 141*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ 142*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ 143*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ 144*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ 145*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ 146*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ 147*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ 148*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ 149*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ 150*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ 151*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ 152*011f5c13SIgor Grinberg /* USB2 EHCI */ 153*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ 154*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ 155*011f5c13SIgor Grinberg MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ 156*011f5c13SIgor Grinberg MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ 157*011f5c13SIgor Grinberg MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ 158*011f5c13SIgor Grinberg MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ 159*011f5c13SIgor Grinberg MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ 160*011f5c13SIgor Grinberg MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ 161*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ 162*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ 163*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ 164*011f5c13SIgor Grinberg MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ 165*011f5c13SIgor Grinberg 166b09bf723SIgor Grinberg /* SYS_BOOT */ 167b09bf723SIgor Grinberg MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/ 168b09bf723SIgor Grinberg MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/ 169b09bf723SIgor Grinberg MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/ 170b09bf723SIgor Grinberg MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/ 171b09bf723SIgor Grinberg MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/ 172b09bf723SIgor Grinberg MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/ 173b09bf723SIgor Grinberg } 174