1 /* 2 * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il> 3 * 4 * Authors: Mike Rapoport <mike@compulab.co.il> 5 * Igor Grinberg <grinberg@compulab.co.il> 6 * 7 * Derived from omap3evm and Beagle Board by 8 * Manikandan Pillai <mani.pillai@ti.com> 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <status_led.h> 17 #include <netdev.h> 18 #include <net.h> 19 #include <i2c.h> 20 #include <usb.h> 21 #include <mmc.h> 22 #include <nand.h> 23 #include <twl4030.h> 24 #include <bmp_layout.h> 25 #include <linux/compiler.h> 26 27 #include <asm/io.h> 28 #include <asm/arch/mem.h> 29 #include <asm/arch/mux.h> 30 #include <asm/arch/mmc_host_def.h> 31 #include <asm/arch/sys_proto.h> 32 #include <asm/mach-types.h> 33 #include <asm/ehci-omap.h> 34 #include <asm/gpio.h> 35 36 #include "../common/eeprom.h" 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 const omap3_sysinfo sysinfo = { 41 DDR_DISCRETE, 42 "CM-T3x board", 43 "NAND", 44 }; 45 46 static u32 gpmc_net_config[GPMC_MAX_REG] = { 47 NET_GPMC_CONFIG1, 48 NET_GPMC_CONFIG2, 49 NET_GPMC_CONFIG3, 50 NET_GPMC_CONFIG4, 51 NET_GPMC_CONFIG5, 52 NET_GPMC_CONFIG6, 53 0 54 }; 55 56 static u32 gpmc_nand_config[GPMC_MAX_REG] = { 57 SMNAND_GPMC_CONFIG1, 58 SMNAND_GPMC_CONFIG2, 59 SMNAND_GPMC_CONFIG3, 60 SMNAND_GPMC_CONFIG4, 61 SMNAND_GPMC_CONFIG5, 62 SMNAND_GPMC_CONFIG6, 63 0, 64 }; 65 66 #ifdef CONFIG_LCD 67 #ifdef CONFIG_CMD_NAND 68 static int splash_load_from_nand(u32 bmp_load_addr) 69 { 70 struct bmp_header *bmp_hdr; 71 int res, splash_screen_nand_offset = 0x100000; 72 size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); 73 74 if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) 75 goto splash_address_too_high; 76 77 res = nand_read_skip_bad(&nand_info[nand_curr_device], 78 splash_screen_nand_offset, &bmp_header_size, 79 NULL, nand_info[nand_curr_device].size, 80 (u_char *)bmp_load_addr); 81 if (res < 0) 82 return res; 83 84 bmp_hdr = (struct bmp_header *)bmp_load_addr; 85 bmp_size = le32_to_cpu(bmp_hdr->file_size); 86 87 if (bmp_load_addr + bmp_size >= gd->start_addr_sp) 88 goto splash_address_too_high; 89 90 return nand_read_skip_bad(&nand_info[nand_curr_device], 91 splash_screen_nand_offset, &bmp_size, 92 NULL, nand_info[nand_curr_device].size, 93 (u_char *)bmp_load_addr); 94 95 splash_address_too_high: 96 printf("Error: splashimage address too high. Data overwrites U-Boot " 97 "and/or placed beyond DRAM boundaries.\n"); 98 99 return -1; 100 } 101 #else 102 static inline int splash_load_from_nand(void) 103 { 104 return -1; 105 } 106 #endif /* CONFIG_CMD_NAND */ 107 108 int splash_screen_prepare(void) 109 { 110 char *env_splashimage_value; 111 u32 bmp_load_addr; 112 113 env_splashimage_value = getenv("splashimage"); 114 if (env_splashimage_value == NULL) 115 return -1; 116 117 bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); 118 if (bmp_load_addr == 0) { 119 printf("Error: bad splashimage address specified\n"); 120 return -1; 121 } 122 123 return splash_load_from_nand(bmp_load_addr); 124 } 125 #endif /* CONFIG_LCD */ 126 127 /* 128 * Routine: board_init 129 * Description: hardware init. 130 */ 131 int board_init(void) 132 { 133 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 134 135 enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0], 136 CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M); 137 138 /* board id for Linux */ 139 if (get_cpu_family() == CPU_OMAP34XX) 140 gd->bd->bi_arch_number = MACH_TYPE_CM_T35; 141 else 142 gd->bd->bi_arch_number = MACH_TYPE_CM_T3730; 143 144 /* boot param addr */ 145 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 146 147 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) 148 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); 149 #endif 150 151 return 0; 152 } 153 154 static u32 cm_t3x_rev; 155 156 /* 157 * Routine: get_board_rev 158 * Description: read system revision 159 */ 160 u32 get_board_rev(void) 161 { 162 if (!cm_t3x_rev) 163 cm_t3x_rev = cl_eeprom_get_board_rev(); 164 165 return cm_t3x_rev; 166 }; 167 168 /* 169 * Routine: misc_init_r 170 * Description: display die ID 171 */ 172 int misc_init_r(void) 173 { 174 u32 board_rev = get_board_rev(); 175 u32 rev_major = board_rev / 100; 176 u32 rev_minor = board_rev - (rev_major * 100); 177 178 if ((rev_minor / 10) * 10 == rev_minor) 179 rev_minor = rev_minor / 10; 180 181 printf("PCB: %u.%u\n", rev_major, rev_minor); 182 dieid_num_r(); 183 184 return 0; 185 } 186 187 /* 188 * Routine: set_muxconf_regs 189 * Description: Setting up the configuration Mux registers specific to the 190 * hardware. Many pins need to be moved from protect to primary 191 * mode. 192 */ 193 static void cm_t3x_set_common_muxconf(void) 194 { 195 /* SDRC */ 196 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ 197 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ 198 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ 199 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ 200 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ 201 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ 202 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ 203 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ 204 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ 205 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ 206 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ 207 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ 208 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ 209 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ 210 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ 211 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ 212 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ 213 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ 214 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ 215 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ 216 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ 217 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ 218 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ 219 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ 220 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ 221 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ 222 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ 223 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ 224 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ 225 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ 226 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ 227 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ 228 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ 229 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ 230 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ 231 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ 232 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ 233 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ 234 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ 235 236 /* GPMC */ 237 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ 238 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ 239 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ 240 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ 241 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ 242 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ 243 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ 244 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ 245 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ 246 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ 247 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ 248 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ 249 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ 250 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ 251 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ 252 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ 253 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ 254 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ 255 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ 256 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ 257 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ 258 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ 259 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ 260 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ 261 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ 262 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ 263 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ 264 265 /* SB-T35 Ethernet */ 266 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ 267 268 /* DVI enable */ 269 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ 270 271 /* DataImage backlight */ 272 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ 273 274 /* CM-T3x Ethernet */ 275 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ 276 MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ 277 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ 278 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ 279 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/ 280 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ 281 MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/ 282 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/ 283 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ 284 285 /* DSS */ 286 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/ 287 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ 288 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ 289 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ 290 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ 291 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ 292 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ 293 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/ 294 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/ 295 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/ 296 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/ 297 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/ 298 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/ 299 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ 300 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ 301 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ 302 303 /* serial interface */ 304 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ 305 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/ 306 307 /* mUSB */ 308 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ 309 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ 310 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ 311 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ 312 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ 313 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ 314 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ 315 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ 316 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ 317 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ 318 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ 319 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ 320 321 /* USB EHCI */ 322 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ 323 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ 324 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ 325 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ 326 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ 327 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ 328 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ 329 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ 330 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ 331 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ 332 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ 333 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ 334 335 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ 336 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ 337 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ 338 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ 339 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ 340 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ 341 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ 342 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ 343 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ 344 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ 345 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ 346 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ 347 348 /* SB_T35_USB_HUB_RESET_GPIO */ 349 MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ 350 351 /* I2C1 */ 352 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ 353 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ 354 /* I2C2 */ 355 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ 356 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ 357 /* I2C3 */ 358 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ 359 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ 360 361 /* control and debug */ 362 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ 363 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ 364 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ 365 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ 366 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ 367 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ 368 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/ 369 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ 370 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ 371 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ 372 373 /* MMC1 */ 374 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ 375 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ 376 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ 377 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ 378 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ 379 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ 380 381 /* SPI */ 382 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ 383 MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ 384 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ 385 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ 386 387 /* display controls */ 388 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ 389 } 390 391 static void cm_t35_set_muxconf(void) 392 { 393 /* DSS */ 394 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ 395 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ 396 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ 397 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ 398 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ 399 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ 400 401 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ 402 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ 403 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ 404 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ 405 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ 406 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ 407 408 /* MMC1 */ 409 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ 410 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ 411 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ 412 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ 413 } 414 415 static void cm_t3730_set_muxconf(void) 416 { 417 /* DSS */ 418 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/ 419 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/ 420 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/ 421 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/ 422 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/ 423 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/ 424 425 MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/ 426 MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/ 427 MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/ 428 MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/ 429 MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/ 430 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/ 431 } 432 433 void set_muxconf_regs(void) 434 { 435 cm_t3x_set_common_muxconf(); 436 437 if (get_cpu_family() == CPU_OMAP34XX) 438 cm_t35_set_muxconf(); 439 else 440 cm_t3730_set_muxconf(); 441 } 442 443 #ifdef CONFIG_GENERIC_MMC 444 int board_mmc_getcd(struct mmc *mmc) 445 { 446 u8 val; 447 448 if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val)) 449 return -1; 450 451 return !(val & 1); 452 } 453 454 int board_mmc_init(bd_t *bis) 455 { 456 return omap_mmc_init(0, 0, 0, -1, 59); 457 } 458 #endif 459 460 /* 461 * Routine: setup_net_chip_gmpc 462 * Description: Setting up the configuration GPMC registers specific to the 463 * Ethernet hardware. 464 */ 465 static void setup_net_chip_gmpc(void) 466 { 467 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 468 469 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], 470 CM_T3X_SMC911X_BASE, GPMC_SIZE_16M); 471 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], 472 SB_T35_SMC911X_BASE, GPMC_SIZE_16M); 473 474 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 475 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 476 477 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 478 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 479 480 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 481 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 482 &ctrl_base->gpmc_nadv_ale); 483 } 484 485 #ifdef CONFIG_SYS_I2C_OMAP34XX 486 /* 487 * Routine: reset_net_chip 488 * Description: reset the Ethernet controller via TPS65930 GPIO 489 */ 490 static void reset_net_chip(void) 491 { 492 /* Set GPIO1 of TPS65930 as output */ 493 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, 494 0x02); 495 /* Send a pulse on the GPIO pin */ 496 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 497 0x02); 498 udelay(1); 499 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09, 500 0x02); 501 mdelay(40); 502 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 503 0x02); 504 mdelay(1); 505 } 506 #else 507 static inline void reset_net_chip(void) {} 508 #endif 509 510 #ifdef CONFIG_SMC911X 511 /* 512 * Routine: handle_mac_address 513 * Description: prepare MAC address for on-board Ethernet. 514 */ 515 static int handle_mac_address(void) 516 { 517 unsigned char enetaddr[6]; 518 int rc; 519 520 rc = eth_getenv_enetaddr("ethaddr", enetaddr); 521 if (rc) 522 return 0; 523 524 rc = cl_eeprom_read_mac_addr(enetaddr); 525 if (rc) 526 return rc; 527 528 if (!is_valid_ether_addr(enetaddr)) 529 return -1; 530 531 return eth_setenv_enetaddr("ethaddr", enetaddr); 532 } 533 534 535 /* 536 * Routine: board_eth_init 537 * Description: initialize module and base-board Ethernet chips 538 */ 539 int board_eth_init(bd_t *bis) 540 { 541 int rc = 0, rc1 = 0; 542 543 setup_net_chip_gmpc(); 544 reset_net_chip(); 545 546 rc1 = handle_mac_address(); 547 if (rc1) 548 printf("No MAC address found! "); 549 550 rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); 551 if (rc1 > 0) 552 rc++; 553 554 rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); 555 if (rc1 > 0) 556 rc++; 557 558 return rc; 559 } 560 #endif 561 562 void __weak get_board_serial(struct tag_serialnr *serialnr) 563 { 564 /* 565 * This corresponds to what happens when we can communicate with the 566 * eeprom but don't get a valid board serial value. 567 */ 568 serialnr->low = 0; 569 serialnr->high = 0; 570 }; 571 572 #ifdef CONFIG_USB_EHCI_OMAP 573 struct omap_usbhs_board_data usbhs_bdata = { 574 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 575 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 576 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 577 }; 578 579 #define SB_T35_USB_HUB_RESET_GPIO 167 580 int ehci_hcd_init(int index, enum usb_init_type init, 581 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 582 { 583 u8 val; 584 int offset; 585 586 if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) { 587 printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset", 588 SB_T35_USB_HUB_RESET_GPIO); 589 return -1; 590 } 591 592 gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0); 593 udelay(10); 594 gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); 595 udelay(1000); 596 597 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; 598 twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); 599 /* Set GPIO6 and GPIO7 of TPS65930 as output */ 600 val |= 0xC0; 601 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val); 602 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; 603 /* Take both PHYs out of reset */ 604 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0); 605 udelay(1); 606 607 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 608 } 609 610 int ehci_hcd_stop(void) 611 { 612 return omap_ehci_hcd_stop(); 613 } 614 #endif /* CONFIG_USB_EHCI_OMAP */ 615