1 /* 2 * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il> 3 * 4 * Authors: Mike Rapoport <mike@compulab.co.il> 5 * Igor Grinberg <grinberg@compulab.co.il> 6 * 7 * Derived from omap3evm and Beagle Board by 8 * Manikandan Pillai <mani.pillai@ti.com> 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <status_led.h> 17 #include <netdev.h> 18 #include <net.h> 19 #include <i2c.h> 20 #include <usb.h> 21 #include <mmc.h> 22 #include <nand.h> 23 #include <twl4030.h> 24 #include <bmp_layout.h> 25 #include <linux/compiler.h> 26 27 #include <asm/io.h> 28 #include <asm/arch/mem.h> 29 #include <asm/arch/mux.h> 30 #include <asm/arch/mmc_host_def.h> 31 #include <asm/arch/sys_proto.h> 32 #include <asm/mach-types.h> 33 #include <asm/ehci-omap.h> 34 #include <asm/gpio.h> 35 36 #include "../common/eeprom.h" 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 const omap3_sysinfo sysinfo = { 41 DDR_DISCRETE, 42 "CM-T3x board", 43 "NAND", 44 }; 45 46 static u32 gpmc_net_config[GPMC_MAX_REG] = { 47 NET_GPMC_CONFIG1, 48 NET_GPMC_CONFIG2, 49 NET_GPMC_CONFIG3, 50 NET_GPMC_CONFIG4, 51 NET_GPMC_CONFIG5, 52 NET_GPMC_CONFIG6, 53 0 54 }; 55 56 static u32 gpmc_nand_config[GPMC_MAX_REG] = { 57 M_NAND_GPMC_CONFIG1, 58 M_NAND_GPMC_CONFIG2, 59 M_NAND_GPMC_CONFIG3, 60 M_NAND_GPMC_CONFIG4, 61 M_NAND_GPMC_CONFIG5, 62 M_NAND_GPMC_CONFIG6, 63 0, 64 }; 65 66 #ifdef CONFIG_LCD 67 #ifdef CONFIG_CMD_NAND 68 static int splash_load_from_nand(u32 bmp_load_addr) 69 { 70 struct bmp_header *bmp_hdr; 71 int res, splash_screen_nand_offset = 0x100000; 72 size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); 73 74 if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) 75 goto splash_address_too_high; 76 77 res = nand_read_skip_bad(&nand_info[nand_curr_device], 78 splash_screen_nand_offset, &bmp_header_size, 79 NULL, nand_info[nand_curr_device].size, 80 (u_char *)bmp_load_addr); 81 if (res < 0) 82 return res; 83 84 bmp_hdr = (struct bmp_header *)bmp_load_addr; 85 bmp_size = le32_to_cpu(bmp_hdr->file_size); 86 87 if (bmp_load_addr + bmp_size >= gd->start_addr_sp) 88 goto splash_address_too_high; 89 90 return nand_read_skip_bad(&nand_info[nand_curr_device], 91 splash_screen_nand_offset, &bmp_size, 92 NULL, nand_info[nand_curr_device].size, 93 (u_char *)bmp_load_addr); 94 95 splash_address_too_high: 96 printf("Error: splashimage address too high. Data overwrites U-Boot " 97 "and/or placed beyond DRAM boundaries.\n"); 98 99 return -1; 100 } 101 #else 102 static inline int splash_load_from_nand(void) 103 { 104 return -1; 105 } 106 #endif /* CONFIG_CMD_NAND */ 107 108 #ifdef CONFIG_SPL_BUILD 109 /* 110 * Routine: get_board_mem_timings 111 * Description: If we use SPL then there is no x-loader nor config header 112 * so we have to setup the DDR timings ourself on both banks. 113 */ 114 void get_board_mem_timings(struct board_sdrc_timings *timings) 115 { 116 timings->mr = MICRON_V_MR_165; 117 timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */ 118 timings->ctrla = MICRON_V_ACTIMA_165; 119 timings->ctrlb = MICRON_V_ACTIMB_165; 120 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 121 } 122 #endif 123 124 int splash_screen_prepare(void) 125 { 126 char *env_splashimage_value; 127 u32 bmp_load_addr; 128 129 env_splashimage_value = getenv("splashimage"); 130 if (env_splashimage_value == NULL) 131 return -1; 132 133 bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); 134 if (bmp_load_addr == 0) { 135 printf("Error: bad splashimage address specified\n"); 136 return -1; 137 } 138 139 return splash_load_from_nand(bmp_load_addr); 140 } 141 #endif /* CONFIG_LCD */ 142 143 /* 144 * Routine: board_init 145 * Description: hardware init. 146 */ 147 int board_init(void) 148 { 149 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 150 151 enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0], 152 CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M); 153 154 /* board id for Linux */ 155 if (get_cpu_family() == CPU_OMAP34XX) 156 gd->bd->bi_arch_number = MACH_TYPE_CM_T35; 157 else 158 gd->bd->bi_arch_number = MACH_TYPE_CM_T3730; 159 160 /* boot param addr */ 161 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 162 163 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) 164 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); 165 #endif 166 167 return 0; 168 } 169 170 static u32 cm_t3x_rev; 171 172 /* 173 * Routine: get_board_rev 174 * Description: read system revision 175 */ 176 u32 get_board_rev(void) 177 { 178 if (!cm_t3x_rev) 179 cm_t3x_rev = cl_eeprom_get_board_rev(); 180 181 return cm_t3x_rev; 182 }; 183 184 /* 185 * Routine: misc_init_r 186 * Description: display die ID 187 */ 188 int misc_init_r(void) 189 { 190 u32 board_rev = get_board_rev(); 191 u32 rev_major = board_rev / 100; 192 u32 rev_minor = board_rev - (rev_major * 100); 193 194 if ((rev_minor / 10) * 10 == rev_minor) 195 rev_minor = rev_minor / 10; 196 197 printf("PCB: %u.%u\n", rev_major, rev_minor); 198 dieid_num_r(); 199 200 return 0; 201 } 202 203 /* 204 * Routine: set_muxconf_regs 205 * Description: Setting up the configuration Mux registers specific to the 206 * hardware. Many pins need to be moved from protect to primary 207 * mode. 208 */ 209 static void cm_t3x_set_common_muxconf(void) 210 { 211 /* SDRC */ 212 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ 213 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ 214 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ 215 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ 216 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ 217 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ 218 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ 219 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ 220 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ 221 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ 222 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ 223 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ 224 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ 225 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ 226 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ 227 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ 228 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ 229 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ 230 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ 231 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ 232 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ 233 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ 234 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ 235 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ 236 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ 237 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ 238 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ 239 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ 240 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ 241 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ 242 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ 243 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ 244 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ 245 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ 246 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ 247 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ 248 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ 249 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ 250 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ 251 252 /* GPMC */ 253 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ 254 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ 255 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ 256 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ 257 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ 258 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ 259 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ 260 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ 261 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ 262 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ 263 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ 264 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ 265 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ 266 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ 267 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ 268 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ 269 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ 270 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ 271 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ 272 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ 273 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ 274 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ 275 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ 276 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ 277 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ 278 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ 279 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ 280 281 /* SB-T35 Ethernet */ 282 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ 283 284 /* DVI enable */ 285 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ 286 287 /* DataImage backlight */ 288 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ 289 290 /* CM-T3x Ethernet */ 291 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ 292 MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ 293 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ 294 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ 295 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/ 296 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ 297 MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/ 298 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/ 299 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ 300 301 /* DSS */ 302 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/ 303 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ 304 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ 305 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ 306 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ 307 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ 308 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ 309 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/ 310 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/ 311 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/ 312 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/ 313 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/ 314 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/ 315 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ 316 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ 317 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ 318 319 /* serial interface */ 320 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ 321 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/ 322 323 /* mUSB */ 324 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ 325 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ 326 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ 327 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ 328 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ 329 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ 330 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ 331 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ 332 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ 333 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ 334 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ 335 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ 336 337 /* USB EHCI */ 338 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ 339 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ 340 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ 341 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ 342 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ 343 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ 344 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ 345 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ 346 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ 347 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ 348 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ 349 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ 350 351 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ 352 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ 353 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ 354 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ 355 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ 356 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ 357 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ 358 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ 359 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ 360 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ 361 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ 362 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ 363 364 /* SB_T35_USB_HUB_RESET_GPIO */ 365 MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ 366 367 /* I2C1 */ 368 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ 369 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ 370 /* I2C2 */ 371 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ 372 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ 373 /* I2C3 */ 374 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ 375 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ 376 377 /* control and debug */ 378 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ 379 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ 380 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ 381 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ 382 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ 383 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ 384 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/ 385 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ 386 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ 387 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ 388 389 /* MMC1 */ 390 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ 391 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ 392 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ 393 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ 394 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ 395 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ 396 397 /* SPI */ 398 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ 399 MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ 400 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ 401 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ 402 403 /* display controls */ 404 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ 405 } 406 407 static void cm_t35_set_muxconf(void) 408 { 409 /* DSS */ 410 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ 411 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ 412 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ 413 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ 414 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ 415 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ 416 417 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ 418 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ 419 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ 420 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ 421 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ 422 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ 423 424 /* MMC1 */ 425 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ 426 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ 427 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ 428 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ 429 } 430 431 static void cm_t3730_set_muxconf(void) 432 { 433 /* DSS */ 434 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/ 435 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/ 436 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/ 437 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/ 438 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/ 439 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/ 440 441 MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/ 442 MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/ 443 MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/ 444 MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/ 445 MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/ 446 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/ 447 } 448 449 void set_muxconf_regs(void) 450 { 451 cm_t3x_set_common_muxconf(); 452 453 if (get_cpu_family() == CPU_OMAP34XX) 454 cm_t35_set_muxconf(); 455 else 456 cm_t3730_set_muxconf(); 457 } 458 459 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 460 int board_mmc_getcd(struct mmc *mmc) 461 { 462 u8 val; 463 464 if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val)) 465 return -1; 466 467 return !(val & 1); 468 } 469 470 int board_mmc_init(bd_t *bis) 471 { 472 return omap_mmc_init(0, 0, 0, -1, 59); 473 } 474 #endif 475 476 /* 477 * Routine: setup_net_chip_gmpc 478 * Description: Setting up the configuration GPMC registers specific to the 479 * Ethernet hardware. 480 */ 481 static void setup_net_chip_gmpc(void) 482 { 483 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 484 485 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], 486 CM_T3X_SMC911X_BASE, GPMC_SIZE_16M); 487 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], 488 SB_T35_SMC911X_BASE, GPMC_SIZE_16M); 489 490 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 491 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 492 493 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 494 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 495 496 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 497 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 498 &ctrl_base->gpmc_nadv_ale); 499 } 500 501 #ifdef CONFIG_SYS_I2C_OMAP34XX 502 /* 503 * Routine: reset_net_chip 504 * Description: reset the Ethernet controller via TPS65930 GPIO 505 */ 506 static void reset_net_chip(void) 507 { 508 /* Set GPIO1 of TPS65930 as output */ 509 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, 510 0x02); 511 /* Send a pulse on the GPIO pin */ 512 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 513 0x02); 514 udelay(1); 515 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09, 516 0x02); 517 mdelay(40); 518 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 519 0x02); 520 mdelay(1); 521 } 522 #else 523 static inline void reset_net_chip(void) {} 524 #endif 525 526 #ifdef CONFIG_SMC911X 527 /* 528 * Routine: handle_mac_address 529 * Description: prepare MAC address for on-board Ethernet. 530 */ 531 static int handle_mac_address(void) 532 { 533 unsigned char enetaddr[6]; 534 int rc; 535 536 rc = eth_getenv_enetaddr("ethaddr", enetaddr); 537 if (rc) 538 return 0; 539 540 rc = cl_eeprom_read_mac_addr(enetaddr); 541 if (rc) 542 return rc; 543 544 if (!is_valid_ether_addr(enetaddr)) 545 return -1; 546 547 return eth_setenv_enetaddr("ethaddr", enetaddr); 548 } 549 550 551 /* 552 * Routine: board_eth_init 553 * Description: initialize module and base-board Ethernet chips 554 */ 555 int board_eth_init(bd_t *bis) 556 { 557 int rc = 0, rc1 = 0; 558 559 setup_net_chip_gmpc(); 560 reset_net_chip(); 561 562 rc1 = handle_mac_address(); 563 if (rc1) 564 printf("No MAC address found! "); 565 566 rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); 567 if (rc1 > 0) 568 rc++; 569 570 rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); 571 if (rc1 > 0) 572 rc++; 573 574 return rc; 575 } 576 #endif 577 578 void __weak get_board_serial(struct tag_serialnr *serialnr) 579 { 580 /* 581 * This corresponds to what happens when we can communicate with the 582 * eeprom but don't get a valid board serial value. 583 */ 584 serialnr->low = 0; 585 serialnr->high = 0; 586 }; 587 588 #ifdef CONFIG_USB_EHCI_OMAP 589 struct omap_usbhs_board_data usbhs_bdata = { 590 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 591 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 592 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 593 }; 594 595 #define SB_T35_USB_HUB_RESET_GPIO 167 596 int ehci_hcd_init(int index, enum usb_init_type init, 597 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 598 { 599 u8 val; 600 int offset; 601 602 if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) { 603 printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset", 604 SB_T35_USB_HUB_RESET_GPIO); 605 return -1; 606 } 607 608 gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0); 609 udelay(10); 610 gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); 611 udelay(1000); 612 613 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; 614 twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); 615 /* Set GPIO6 and GPIO7 of TPS65930 as output */ 616 val |= 0xC0; 617 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val); 618 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; 619 /* Take both PHYs out of reset */ 620 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0); 621 udelay(1); 622 623 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 624 } 625 626 int ehci_hcd_stop(void) 627 { 628 return omap_ehci_hcd_stop(); 629 } 630 #endif /* CONFIG_USB_EHCI_OMAP */ 631