1 /* 2 * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il> 3 * 4 * Authors: Mike Rapoport <mike@compulab.co.il> 5 * Igor Grinberg <grinberg@compulab.co.il> 6 * 7 * Derived from omap3evm and Beagle Board by 8 * Manikandan Pillai <mani.pillai@ti.com> 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <status_led.h> 17 #include <netdev.h> 18 #include <net.h> 19 #include <i2c.h> 20 #include <usb.h> 21 #include <mmc.h> 22 #include <nand.h> 23 #include <twl4030.h> 24 #include <bmp_layout.h> 25 #include <linux/compiler.h> 26 27 #include <asm/io.h> 28 #include <asm/arch/mem.h> 29 #include <asm/arch/mux.h> 30 #include <asm/arch/mmc_host_def.h> 31 #include <asm/arch/sys_proto.h> 32 #include <asm/mach-types.h> 33 #include <asm/ehci-omap.h> 34 #include <asm/gpio.h> 35 36 #include "../common/eeprom.h" 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 const omap3_sysinfo sysinfo = { 41 DDR_DISCRETE, 42 "CM-T3x board", 43 "NAND", 44 }; 45 46 static u32 gpmc_net_config[GPMC_MAX_REG] = { 47 NET_GPMC_CONFIG1, 48 NET_GPMC_CONFIG2, 49 NET_GPMC_CONFIG3, 50 NET_GPMC_CONFIG4, 51 NET_GPMC_CONFIG5, 52 NET_GPMC_CONFIG6, 53 0 54 }; 55 56 #ifdef CONFIG_LCD 57 #ifdef CONFIG_CMD_NAND 58 static int splash_load_from_nand(u32 bmp_load_addr) 59 { 60 struct bmp_header *bmp_hdr; 61 int res, splash_screen_nand_offset = 0x100000; 62 size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); 63 64 if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) 65 goto splash_address_too_high; 66 67 res = nand_read_skip_bad(&nand_info[nand_curr_device], 68 splash_screen_nand_offset, &bmp_header_size, 69 NULL, nand_info[nand_curr_device].size, 70 (u_char *)bmp_load_addr); 71 if (res < 0) 72 return res; 73 74 bmp_hdr = (struct bmp_header *)bmp_load_addr; 75 bmp_size = le32_to_cpu(bmp_hdr->file_size); 76 77 if (bmp_load_addr + bmp_size >= gd->start_addr_sp) 78 goto splash_address_too_high; 79 80 return nand_read_skip_bad(&nand_info[nand_curr_device], 81 splash_screen_nand_offset, &bmp_size, 82 NULL, nand_info[nand_curr_device].size, 83 (u_char *)bmp_load_addr); 84 85 splash_address_too_high: 86 printf("Error: splashimage address too high. Data overwrites U-Boot " 87 "and/or placed beyond DRAM boundaries.\n"); 88 89 return -1; 90 } 91 #else 92 static inline int splash_load_from_nand(void) 93 { 94 return -1; 95 } 96 #endif /* CONFIG_CMD_NAND */ 97 98 #ifdef CONFIG_SPL_BUILD 99 /* 100 * Routine: get_board_mem_timings 101 * Description: If we use SPL then there is no x-loader nor config header 102 * so we have to setup the DDR timings ourself on both banks. 103 */ 104 void get_board_mem_timings(struct board_sdrc_timings *timings) 105 { 106 timings->mr = MICRON_V_MR_165; 107 timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */ 108 timings->ctrla = MICRON_V_ACTIMA_165; 109 timings->ctrlb = MICRON_V_ACTIMB_165; 110 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 111 } 112 #endif 113 114 int splash_screen_prepare(void) 115 { 116 char *env_splashimage_value; 117 u32 bmp_load_addr; 118 119 env_splashimage_value = getenv("splashimage"); 120 if (env_splashimage_value == NULL) 121 return -1; 122 123 bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); 124 if (bmp_load_addr == 0) { 125 printf("Error: bad splashimage address specified\n"); 126 return -1; 127 } 128 129 return splash_load_from_nand(bmp_load_addr); 130 } 131 #endif /* CONFIG_LCD */ 132 133 /* 134 * Routine: board_init 135 * Description: hardware init. 136 */ 137 int board_init(void) 138 { 139 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 140 141 /* board id for Linux */ 142 if (get_cpu_family() == CPU_OMAP34XX) 143 gd->bd->bi_arch_number = MACH_TYPE_CM_T35; 144 else 145 gd->bd->bi_arch_number = MACH_TYPE_CM_T3730; 146 147 /* boot param addr */ 148 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 149 150 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) 151 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); 152 #endif 153 154 return 0; 155 } 156 157 static u32 cm_t3x_rev; 158 159 /* 160 * Routine: get_board_rev 161 * Description: read system revision 162 */ 163 u32 get_board_rev(void) 164 { 165 if (!cm_t3x_rev) 166 cm_t3x_rev = cl_eeprom_get_board_rev(); 167 168 return cm_t3x_rev; 169 }; 170 171 /* 172 * Routine: misc_init_r 173 * Description: display die ID 174 */ 175 int misc_init_r(void) 176 { 177 u32 board_rev = get_board_rev(); 178 u32 rev_major = board_rev / 100; 179 u32 rev_minor = board_rev - (rev_major * 100); 180 181 if ((rev_minor / 10) * 10 == rev_minor) 182 rev_minor = rev_minor / 10; 183 184 printf("PCB: %u.%u\n", rev_major, rev_minor); 185 dieid_num_r(); 186 187 return 0; 188 } 189 190 /* 191 * Routine: set_muxconf_regs 192 * Description: Setting up the configuration Mux registers specific to the 193 * hardware. Many pins need to be moved from protect to primary 194 * mode. 195 */ 196 static void cm_t3x_set_common_muxconf(void) 197 { 198 /* SDRC */ 199 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ 200 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ 201 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ 202 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ 203 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ 204 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ 205 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ 206 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ 207 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ 208 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ 209 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ 210 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ 211 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ 212 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ 213 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ 214 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ 215 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ 216 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ 217 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ 218 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ 219 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ 220 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ 221 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ 222 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ 223 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ 224 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ 225 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ 226 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ 227 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ 228 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ 229 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ 230 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ 231 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ 232 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ 233 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ 234 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ 235 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ 236 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ 237 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ 238 239 /* GPMC */ 240 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ 241 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ 242 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ 243 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ 244 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ 245 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ 246 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ 247 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ 248 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ 249 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ 250 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ 251 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ 252 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ 253 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ 254 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ 255 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ 256 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ 257 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ 258 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ 259 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ 260 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ 261 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ 262 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ 263 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ 264 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ 265 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ 266 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ 267 268 /* SB-T35 Ethernet */ 269 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ 270 271 /* DVI enable */ 272 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ 273 274 /* DataImage backlight */ 275 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ 276 277 /* CM-T3x Ethernet */ 278 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ 279 MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ 280 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ 281 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ 282 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/ 283 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ 284 MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/ 285 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/ 286 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ 287 288 /* DSS */ 289 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/ 290 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ 291 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ 292 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ 293 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ 294 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ 295 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ 296 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/ 297 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/ 298 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/ 299 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/ 300 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/ 301 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/ 302 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ 303 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ 304 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ 305 306 /* serial interface */ 307 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ 308 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/ 309 310 /* mUSB */ 311 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ 312 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ 313 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ 314 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ 315 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ 316 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ 317 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ 318 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ 319 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ 320 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ 321 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ 322 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ 323 324 /* USB EHCI */ 325 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ 326 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ 327 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ 328 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ 329 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ 330 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ 331 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ 332 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ 333 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ 334 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ 335 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ 336 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ 337 338 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ 339 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ 340 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ 341 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ 342 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ 343 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ 344 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ 345 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ 346 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ 347 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ 348 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ 349 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ 350 351 /* SB_T35_USB_HUB_RESET_GPIO */ 352 MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ 353 354 /* I2C1 */ 355 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ 356 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ 357 /* I2C2 */ 358 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ 359 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ 360 /* I2C3 */ 361 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ 362 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ 363 364 /* control and debug */ 365 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ 366 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ 367 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ 368 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ 369 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ 370 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ 371 MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/ 372 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ 373 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ 374 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ 375 376 /* MMC1 */ 377 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ 378 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ 379 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ 380 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ 381 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ 382 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ 383 384 /* SPI */ 385 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ 386 MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ 387 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ 388 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ 389 390 /* display controls */ 391 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ 392 } 393 394 static void cm_t35_set_muxconf(void) 395 { 396 /* DSS */ 397 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ 398 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ 399 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ 400 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ 401 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ 402 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ 403 404 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ 405 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ 406 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ 407 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ 408 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ 409 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ 410 411 /* MMC1 */ 412 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ 413 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ 414 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ 415 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ 416 } 417 418 static void cm_t3730_set_muxconf(void) 419 { 420 /* DSS */ 421 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/ 422 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/ 423 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/ 424 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/ 425 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/ 426 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/ 427 428 MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/ 429 MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/ 430 MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/ 431 MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/ 432 MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/ 433 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/ 434 } 435 436 void set_muxconf_regs(void) 437 { 438 cm_t3x_set_common_muxconf(); 439 440 if (get_cpu_family() == CPU_OMAP34XX) 441 cm_t35_set_muxconf(); 442 else 443 cm_t3730_set_muxconf(); 444 } 445 446 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 447 #define SB_T35_WP_GPIO 59 448 449 int board_mmc_getcd(struct mmc *mmc) 450 { 451 u8 val; 452 453 if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val)) 454 return -1; 455 456 return !(val & 1); 457 } 458 459 int board_mmc_init(bd_t *bis) 460 { 461 return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO); 462 } 463 #endif 464 465 /* 466 * Routine: setup_net_chip_gmpc 467 * Description: Setting up the configuration GPMC registers specific to the 468 * Ethernet hardware. 469 */ 470 static void setup_net_chip_gmpc(void) 471 { 472 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 473 474 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], 475 CM_T3X_SMC911X_BASE, GPMC_SIZE_16M); 476 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], 477 SB_T35_SMC911X_BASE, GPMC_SIZE_16M); 478 479 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 480 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 481 482 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 483 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 484 485 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 486 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 487 &ctrl_base->gpmc_nadv_ale); 488 } 489 490 #ifdef CONFIG_SYS_I2C_OMAP34XX 491 /* 492 * Routine: reset_net_chip 493 * Description: reset the Ethernet controller via TPS65930 GPIO 494 */ 495 static void reset_net_chip(void) 496 { 497 /* Set GPIO1 of TPS65930 as output */ 498 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, 499 0x02); 500 /* Send a pulse on the GPIO pin */ 501 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 502 0x02); 503 udelay(1); 504 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09, 505 0x02); 506 mdelay(40); 507 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 508 0x02); 509 mdelay(1); 510 } 511 #else 512 static inline void reset_net_chip(void) {} 513 #endif 514 515 #ifdef CONFIG_SMC911X 516 /* 517 * Routine: handle_mac_address 518 * Description: prepare MAC address for on-board Ethernet. 519 */ 520 static int handle_mac_address(void) 521 { 522 unsigned char enetaddr[6]; 523 int rc; 524 525 rc = eth_getenv_enetaddr("ethaddr", enetaddr); 526 if (rc) 527 return 0; 528 529 rc = cl_eeprom_read_mac_addr(enetaddr); 530 if (rc) 531 return rc; 532 533 if (!is_valid_ether_addr(enetaddr)) 534 return -1; 535 536 return eth_setenv_enetaddr("ethaddr", enetaddr); 537 } 538 539 540 /* 541 * Routine: board_eth_init 542 * Description: initialize module and base-board Ethernet chips 543 */ 544 int board_eth_init(bd_t *bis) 545 { 546 int rc = 0, rc1 = 0; 547 548 setup_net_chip_gmpc(); 549 reset_net_chip(); 550 551 rc1 = handle_mac_address(); 552 if (rc1) 553 printf("No MAC address found! "); 554 555 rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); 556 if (rc1 > 0) 557 rc++; 558 559 rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); 560 if (rc1 > 0) 561 rc++; 562 563 return rc; 564 } 565 #endif 566 567 void __weak get_board_serial(struct tag_serialnr *serialnr) 568 { 569 /* 570 * This corresponds to what happens when we can communicate with the 571 * eeprom but don't get a valid board serial value. 572 */ 573 serialnr->low = 0; 574 serialnr->high = 0; 575 }; 576 577 #ifdef CONFIG_USB_EHCI_OMAP 578 struct omap_usbhs_board_data usbhs_bdata = { 579 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 580 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 581 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 582 }; 583 584 #define SB_T35_USB_HUB_RESET_GPIO 167 585 int ehci_hcd_init(int index, enum usb_init_type init, 586 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 587 { 588 u8 val; 589 int offset; 590 591 if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) { 592 printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset", 593 SB_T35_USB_HUB_RESET_GPIO); 594 return -1; 595 } 596 597 gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0); 598 udelay(10); 599 gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); 600 udelay(1000); 601 602 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; 603 twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); 604 /* Set GPIO6 and GPIO7 of TPS65930 as output */ 605 val |= 0xC0; 606 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val); 607 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; 608 /* Take both PHYs out of reset */ 609 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0); 610 udelay(1); 611 612 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 613 } 614 615 int ehci_hcd_stop(void) 616 { 617 return omap_ehci_hcd_stop(); 618 } 619 #endif /* CONFIG_USB_EHCI_OMAP */ 620