1 /* 2 * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il> 3 * 4 * Authors: Mike Rapoport <mike@compulab.co.il> 5 * Igor Grinberg <grinberg@compulab.co.il> 6 * 7 * Derived from omap3evm and Beagle Board by 8 * Manikandan Pillai <mani.pillai@ti.com> 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <status_led.h> 17 #include <netdev.h> 18 #include <net.h> 19 #include <i2c.h> 20 #include <usb.h> 21 #include <mmc.h> 22 #include <twl4030.h> 23 #include <linux/compiler.h> 24 25 #include <asm/io.h> 26 #include <asm/errno.h> 27 #include <asm/arch/mem.h> 28 #include <asm/arch/mux.h> 29 #include <asm/arch/mmc_host_def.h> 30 #include <asm/arch/sys_proto.h> 31 #include <asm/mach-types.h> 32 #include <asm/ehci-omap.h> 33 #include <asm/gpio.h> 34 35 #include "../common/common.h" 36 #include "../common/eeprom.h" 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 const omap3_sysinfo sysinfo = { 41 DDR_DISCRETE, 42 "CM-T3x board", 43 "NAND", 44 }; 45 46 #ifdef CONFIG_SPL_BUILD 47 /* 48 * Routine: get_board_mem_timings 49 * Description: If we use SPL then there is no x-loader nor config header 50 * so we have to setup the DDR timings ourself on both banks. 51 */ 52 void get_board_mem_timings(struct board_sdrc_timings *timings) 53 { 54 timings->mr = MICRON_V_MR_165; 55 timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */ 56 timings->ctrla = MICRON_V_ACTIMA_165; 57 timings->ctrlb = MICRON_V_ACTIMB_165; 58 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 59 } 60 #endif 61 62 #define CM_T35_SPLASH_NAND_OFFSET 0x100000 63 64 int splash_screen_prepare(void) 65 { 66 return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET); 67 } 68 69 /* 70 * Routine: board_init 71 * Description: hardware init. 72 */ 73 int board_init(void) 74 { 75 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 76 77 /* board id for Linux */ 78 if (get_cpu_family() == CPU_OMAP34XX) 79 gd->bd->bi_arch_number = MACH_TYPE_CM_T35; 80 else 81 gd->bd->bi_arch_number = MACH_TYPE_CM_T3730; 82 83 /* boot param addr */ 84 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 85 86 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) 87 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); 88 #endif 89 90 return 0; 91 } 92 93 /* 94 * Routine: get_board_rev 95 * Description: read system revision 96 */ 97 u32 get_board_rev(void) 98 { 99 return cl_eeprom_get_board_rev(); 100 }; 101 102 int misc_init_r(void) 103 { 104 cl_print_pcb_info(); 105 dieid_num_r(); 106 107 return 0; 108 } 109 110 /* 111 * Routine: set_muxconf_regs 112 * Description: Setting up the configuration Mux registers specific to the 113 * hardware. Many pins need to be moved from protect to primary 114 * mode. 115 */ 116 static void cm_t3x_set_common_muxconf(void) 117 { 118 /* SDRC */ 119 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ 120 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ 121 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ 122 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ 123 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ 124 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ 125 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ 126 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ 127 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ 128 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ 129 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ 130 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ 131 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ 132 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ 133 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ 134 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ 135 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ 136 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ 137 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ 138 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ 139 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ 140 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ 141 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ 142 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ 143 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ 144 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ 145 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ 146 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ 147 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ 148 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ 149 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ 150 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ 151 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ 152 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ 153 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ 154 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ 155 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ 156 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ 157 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ 158 159 /* GPMC */ 160 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ 161 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ 162 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ 163 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ 164 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ 165 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ 166 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ 167 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ 168 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ 169 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ 170 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ 171 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ 172 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ 173 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ 174 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ 175 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ 176 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ 177 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ 178 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ 179 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ 180 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ 181 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ 182 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ 183 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ 184 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ 185 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ 186 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ 187 188 /* SB-T35 Ethernet */ 189 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ 190 191 /* DVI enable */ 192 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ 193 194 /* DataImage backlight */ 195 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ 196 197 /* CM-T3x Ethernet */ 198 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ 199 MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ 200 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ 201 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ 202 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/ 203 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ 204 MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/ 205 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/ 206 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ 207 208 /* DSS */ 209 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/ 210 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ 211 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ 212 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ 213 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ 214 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ 215 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ 216 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/ 217 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/ 218 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/ 219 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/ 220 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/ 221 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/ 222 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ 223 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ 224 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ 225 226 /* serial interface */ 227 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ 228 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/ 229 230 /* mUSB */ 231 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ 232 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ 233 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ 234 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ 235 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ 236 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ 237 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ 238 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ 239 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ 240 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ 241 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ 242 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ 243 244 /* USB EHCI */ 245 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ 246 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ 247 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ 248 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ 249 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ 250 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ 251 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ 252 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ 253 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ 254 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ 255 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ 256 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ 257 258 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ 259 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ 260 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ 261 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ 262 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ 263 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ 264 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ 265 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ 266 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ 267 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ 268 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ 269 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ 270 271 /* SB_T35_USB_HUB_RESET_GPIO */ 272 MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ 273 274 /* I2C1 */ 275 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ 276 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ 277 /* I2C2 */ 278 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ 279 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ 280 /* I2C3 */ 281 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ 282 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ 283 284 /* control and debug */ 285 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ 286 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ 287 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ 288 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ 289 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ 290 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ 291 MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/ 292 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ 293 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ 294 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ 295 296 /* MMC1 */ 297 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ 298 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ 299 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ 300 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ 301 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ 302 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ 303 304 /* SPI */ 305 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ 306 MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ 307 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ 308 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ 309 310 /* display controls */ 311 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ 312 } 313 314 static void cm_t35_set_muxconf(void) 315 { 316 /* DSS */ 317 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ 318 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ 319 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ 320 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ 321 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ 322 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ 323 324 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ 325 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ 326 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ 327 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ 328 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ 329 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ 330 331 /* MMC1 */ 332 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ 333 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ 334 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ 335 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ 336 } 337 338 static void cm_t3730_set_muxconf(void) 339 { 340 /* DSS */ 341 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/ 342 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/ 343 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/ 344 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/ 345 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/ 346 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/ 347 348 MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/ 349 MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/ 350 MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/ 351 MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/ 352 MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/ 353 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/ 354 } 355 356 void set_muxconf_regs(void) 357 { 358 cm_t3x_set_common_muxconf(); 359 360 if (get_cpu_family() == CPU_OMAP34XX) 361 cm_t35_set_muxconf(); 362 else 363 cm_t3730_set_muxconf(); 364 } 365 366 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 367 #define SB_T35_WP_GPIO 59 368 369 int board_mmc_getcd(struct mmc *mmc) 370 { 371 u8 val; 372 373 if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val)) 374 return -1; 375 376 return !(val & 1); 377 } 378 379 int board_mmc_init(bd_t *bis) 380 { 381 return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO); 382 } 383 #endif 384 385 #ifdef CONFIG_SYS_I2C_OMAP34XX 386 /* 387 * Routine: reset_net_chip 388 * Description: reset the Ethernet controller via TPS65930 GPIO 389 */ 390 static int cm_t3x_reset_net_chip(int gpio) 391 { 392 /* Set GPIO1 of TPS65930 as output */ 393 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, 394 0x02); 395 /* Send a pulse on the GPIO pin */ 396 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 397 0x02); 398 udelay(1); 399 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09, 400 0x02); 401 mdelay(40); 402 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 403 0x02); 404 mdelay(1); 405 return 0; 406 } 407 #else 408 static inline int cm_t3x_reset_net_chip(int gpio) { return 0; } 409 #endif 410 411 #ifdef CONFIG_SMC911X 412 /* 413 * Routine: handle_mac_address 414 * Description: prepare MAC address for on-board Ethernet. 415 */ 416 static int handle_mac_address(void) 417 { 418 unsigned char enetaddr[6]; 419 int rc; 420 421 rc = eth_getenv_enetaddr("ethaddr", enetaddr); 422 if (rc) 423 return 0; 424 425 rc = cl_eeprom_read_mac_addr(enetaddr); 426 if (rc) 427 return rc; 428 429 if (!is_valid_ether_addr(enetaddr)) 430 return -1; 431 432 return eth_setenv_enetaddr("ethaddr", enetaddr); 433 } 434 435 /* 436 * Routine: board_eth_init 437 * Description: initialize module and base-board Ethernet chips 438 */ 439 int board_eth_init(bd_t *bis) 440 { 441 int rc = 0, rc1 = 0; 442 443 rc1 = handle_mac_address(); 444 if (rc1) 445 printf("No MAC address found! "); 446 447 rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE, 448 cm_t3x_reset_net_chip, -EINVAL); 449 if (rc1 > 0) 450 rc++; 451 452 rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL); 453 if (rc1 > 0) 454 rc++; 455 456 return rc; 457 } 458 #endif 459 460 #ifdef CONFIG_USB_EHCI_OMAP 461 struct omap_usbhs_board_data usbhs_bdata = { 462 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 463 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 464 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 465 }; 466 467 #define SB_T35_USB_HUB_RESET_GPIO 167 468 int ehci_hcd_init(int index, enum usb_init_type init, 469 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 470 { 471 u8 val; 472 int offset; 473 474 cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); 475 476 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; 477 twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); 478 /* Set GPIO6 and GPIO7 of TPS65930 as output */ 479 val |= 0xC0; 480 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val); 481 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; 482 /* Take both PHYs out of reset */ 483 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0); 484 udelay(1); 485 486 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 487 } 488 489 int ehci_hcd_stop(void) 490 { 491 cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); 492 return omap_ehci_hcd_stop(); 493 } 494 #endif /* CONFIG_USB_EHCI_OMAP */ 495