1 /* 2 * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il> 3 * 4 * Authors: Mike Rapoport <mike@compulab.co.il> 5 * Igor Grinberg <grinberg@compulab.co.il> 6 * 7 * Derived from omap3evm and Beagle Board by 8 * Manikandan Pillai <mani.pillai@ti.com> 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <environment.h> 17 #include <status_led.h> 18 #include <netdev.h> 19 #include <net.h> 20 #include <i2c.h> 21 #include <usb.h> 22 #include <mmc.h> 23 #include <splash.h> 24 #include <twl4030.h> 25 #include <linux/compiler.h> 26 27 #include <asm/io.h> 28 #include <linux/errno.h> 29 #include <asm/arch/mem.h> 30 #include <asm/arch/mux.h> 31 #include <asm/arch/mmc_host_def.h> 32 #include <asm/arch/sys_proto.h> 33 #include <asm/mach-types.h> 34 #include <asm/ehci-omap.h> 35 #include <asm/gpio.h> 36 37 #include "../common/common.h" 38 #include "../common/eeprom.h" 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 const omap3_sysinfo sysinfo = { 43 DDR_DISCRETE, 44 "CM-T3x board", 45 "NAND", 46 }; 47 48 #ifdef CONFIG_SPL_BUILD 49 /* 50 * Routine: get_board_mem_timings 51 * Description: If we use SPL then there is no x-loader nor config header 52 * so we have to setup the DDR timings ourself on both banks. 53 */ 54 void get_board_mem_timings(struct board_sdrc_timings *timings) 55 { 56 timings->mr = MICRON_V_MR_165; 57 timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */ 58 timings->ctrla = MICRON_V_ACTIMA_165; 59 timings->ctrlb = MICRON_V_ACTIMB_165; 60 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 61 } 62 #endif 63 64 struct splash_location splash_locations[] = { 65 { 66 .name = "nand", 67 .storage = SPLASH_STORAGE_NAND, 68 .flags = SPLASH_STORAGE_RAW, 69 .offset = 0x100000, 70 }, 71 }; 72 73 int splash_screen_prepare(void) 74 { 75 return splash_source_load(splash_locations, 76 ARRAY_SIZE(splash_locations)); 77 } 78 79 /* 80 * Routine: board_init 81 * Description: hardware init. 82 */ 83 int board_init(void) 84 { 85 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 86 87 /* board id for Linux */ 88 if (get_cpu_family() == CPU_OMAP34XX) 89 gd->bd->bi_arch_number = MACH_TYPE_CM_T35; 90 else 91 gd->bd->bi_arch_number = MACH_TYPE_CM_T3730; 92 93 /* boot param addr */ 94 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 95 96 #if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) 97 status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON); 98 #endif 99 100 return 0; 101 } 102 103 /* 104 * Routine: get_board_rev 105 * Description: read system revision 106 */ 107 u32 get_board_rev(void) 108 { 109 return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS); 110 }; 111 112 int misc_init_r(void) 113 { 114 cl_print_pcb_info(); 115 omap_die_id_display(); 116 117 return 0; 118 } 119 120 /* 121 * Routine: set_muxconf_regs 122 * Description: Setting up the configuration Mux registers specific to the 123 * hardware. Many pins need to be moved from protect to primary 124 * mode. 125 */ 126 static void cm_t3x_set_common_muxconf(void) 127 { 128 /* SDRC */ 129 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ 130 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ 131 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ 132 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ 133 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ 134 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ 135 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ 136 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ 137 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ 138 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ 139 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ 140 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ 141 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ 142 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ 143 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ 144 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ 145 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ 146 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ 147 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ 148 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ 149 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ 150 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ 151 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ 152 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ 153 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ 154 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ 155 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ 156 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ 157 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ 158 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ 159 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ 160 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ 161 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ 162 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ 163 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ 164 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ 165 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ 166 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ 167 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ 168 169 /* GPMC */ 170 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ 171 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ 172 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ 173 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ 174 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ 175 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ 176 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ 177 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ 178 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ 179 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ 180 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ 181 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ 182 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ 183 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ 184 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ 185 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ 186 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ 187 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ 188 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ 189 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ 190 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ 191 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ 192 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ 193 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ 194 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ 195 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ 196 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ 197 198 /* SB-T35 Ethernet */ 199 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ 200 201 /* DVI enable */ 202 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ 203 204 /* DataImage backlight */ 205 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ 206 207 /* CM-T3x Ethernet */ 208 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ 209 MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ 210 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ 211 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ 212 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/ 213 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ 214 MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/ 215 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/ 216 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ 217 218 /* DSS */ 219 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/ 220 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ 221 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ 222 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ 223 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ 224 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ 225 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ 226 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/ 227 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/ 228 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/ 229 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/ 230 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/ 231 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/ 232 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ 233 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ 234 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ 235 236 /* serial interface */ 237 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ 238 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/ 239 240 /* mUSB */ 241 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ 242 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ 243 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ 244 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ 245 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ 246 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ 247 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ 248 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ 249 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ 250 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ 251 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ 252 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ 253 254 /* USB EHCI */ 255 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ 256 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ 257 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ 258 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ 259 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ 260 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ 261 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ 262 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ 263 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ 264 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ 265 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ 266 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ 267 268 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ 269 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ 270 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ 271 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ 272 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ 273 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ 274 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ 275 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ 276 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ 277 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ 278 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ 279 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ 280 281 /* SB_T35_USB_HUB_RESET_GPIO */ 282 MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ 283 284 /* I2C1 */ 285 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ 286 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ 287 /* I2C2 */ 288 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ 289 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ 290 /* I2C3 */ 291 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ 292 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ 293 294 /* control and debug */ 295 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ 296 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ 297 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ 298 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ 299 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ 300 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ 301 MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/ 302 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ 303 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ 304 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ 305 306 /* MMC1 */ 307 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ 308 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ 309 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ 310 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ 311 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ 312 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ 313 314 /* SPI */ 315 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ 316 MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ 317 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ 318 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ 319 320 /* display controls */ 321 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ 322 } 323 324 static void cm_t35_set_muxconf(void) 325 { 326 /* DSS */ 327 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ 328 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ 329 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ 330 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ 331 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ 332 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ 333 334 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ 335 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ 336 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ 337 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ 338 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ 339 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ 340 341 /* MMC1 */ 342 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ 343 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ 344 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ 345 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ 346 } 347 348 static void cm_t3730_set_muxconf(void) 349 { 350 /* DSS */ 351 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/ 352 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/ 353 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/ 354 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/ 355 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/ 356 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/ 357 358 MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/ 359 MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/ 360 MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/ 361 MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/ 362 MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/ 363 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/ 364 } 365 366 void set_muxconf_regs(void) 367 { 368 cm_t3x_set_common_muxconf(); 369 370 if (get_cpu_family() == CPU_OMAP34XX) 371 cm_t35_set_muxconf(); 372 else 373 cm_t3730_set_muxconf(); 374 } 375 376 #if defined(CONFIG_MMC) 377 #define SB_T35_WP_GPIO 59 378 379 int board_mmc_getcd(struct mmc *mmc) 380 { 381 u8 val; 382 383 if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val)) 384 return -1; 385 386 return !(val & 1); 387 } 388 389 int board_mmc_init(bd_t *bis) 390 { 391 return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO); 392 } 393 #endif 394 395 #if defined(CONFIG_MMC) 396 void board_mmc_power_init(void) 397 { 398 twl4030_power_mmc_init(0); 399 } 400 #endif 401 402 #ifdef CONFIG_SYS_I2C_OMAP24XX 403 /* 404 * Routine: reset_net_chip 405 * Description: reset the Ethernet controller via TPS65930 GPIO 406 */ 407 static int cm_t3x_reset_net_chip(int gpio) 408 { 409 /* Set GPIO1 of TPS65930 as output */ 410 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, 411 0x02); 412 /* Send a pulse on the GPIO pin */ 413 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 414 0x02); 415 udelay(1); 416 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09, 417 0x02); 418 mdelay(40); 419 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 420 0x02); 421 mdelay(1); 422 return 0; 423 } 424 #else 425 static inline int cm_t3x_reset_net_chip(int gpio) { return 0; } 426 #endif 427 428 #ifdef CONFIG_SMC911X 429 /* 430 * Routine: handle_mac_address 431 * Description: prepare MAC address for on-board Ethernet. 432 */ 433 static int handle_mac_address(void) 434 { 435 unsigned char enetaddr[6]; 436 int rc; 437 438 rc = eth_env_get_enetaddr("ethaddr", enetaddr); 439 if (rc) 440 return 0; 441 442 rc = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); 443 if (rc) 444 return rc; 445 446 if (!is_valid_ethaddr(enetaddr)) 447 return -1; 448 449 return eth_env_set_enetaddr("ethaddr", enetaddr); 450 } 451 452 /* 453 * Routine: board_eth_init 454 * Description: initialize module and base-board Ethernet chips 455 */ 456 #define SB_T35_SMC911X_BASE (CONFIG_SMC911X_BASE + SZ_16M) 457 int board_eth_init(bd_t *bis) 458 { 459 int rc = 0, rc1 = 0; 460 461 rc1 = handle_mac_address(); 462 if (rc1) 463 printf("No MAC address found! "); 464 465 rc1 = cl_omap3_smc911x_init(0, 5, CONFIG_SMC911X_BASE, 466 cm_t3x_reset_net_chip, -EINVAL); 467 if (rc1 > 0) 468 rc++; 469 470 rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL); 471 if (rc1 > 0) 472 rc++; 473 474 return rc; 475 } 476 #endif 477 478 #ifdef CONFIG_USB_EHCI_OMAP 479 struct omap_usbhs_board_data usbhs_bdata = { 480 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 481 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 482 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 483 }; 484 485 #define SB_T35_USB_HUB_RESET_GPIO 167 486 int ehci_hcd_init(int index, enum usb_init_type init, 487 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 488 { 489 u8 val; 490 int offset; 491 492 cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); 493 494 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; 495 twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); 496 /* Set GPIO6 and GPIO7 of TPS65930 as output */ 497 val |= 0xC0; 498 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val); 499 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; 500 /* Take both PHYs out of reset */ 501 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0); 502 udelay(1); 503 504 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 505 } 506 507 int ehci_hcd_stop(void) 508 { 509 cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); 510 return omap_ehci_hcd_stop(); 511 } 512 #endif /* CONFIG_USB_EHCI_OMAP */ 513