1 /* 2 * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il> 3 * 4 * Authors: Mike Rapoport <mike@compulab.co.il> 5 * Igor Grinberg <grinberg@compulab.co.il> 6 * 7 * Derived from omap3evm and Beagle Board by 8 * Manikandan Pillai <mani.pillai@ti.com> 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <status_led.h> 17 #include <netdev.h> 18 #include <net.h> 19 #include <i2c.h> 20 #include <usb.h> 21 #include <mmc.h> 22 #include <nand.h> 23 #include <twl4030.h> 24 #include <bmp_layout.h> 25 #include <linux/compiler.h> 26 27 #include <asm/io.h> 28 #include <asm/arch/mem.h> 29 #include <asm/arch/mux.h> 30 #include <asm/arch/mmc_host_def.h> 31 #include <asm/arch/sys_proto.h> 32 #include <asm/mach-types.h> 33 #include <asm/ehci-omap.h> 34 #include <asm/gpio.h> 35 36 #include "eeprom.h" 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 const omap3_sysinfo sysinfo = { 41 DDR_DISCRETE, 42 "CM-T3x board", 43 "NAND", 44 }; 45 46 static u32 gpmc_net_config[GPMC_MAX_REG] = { 47 NET_GPMC_CONFIG1, 48 NET_GPMC_CONFIG2, 49 NET_GPMC_CONFIG3, 50 NET_GPMC_CONFIG4, 51 NET_GPMC_CONFIG5, 52 NET_GPMC_CONFIG6, 53 0 54 }; 55 56 static u32 gpmc_nand_config[GPMC_MAX_REG] = { 57 SMNAND_GPMC_CONFIG1, 58 SMNAND_GPMC_CONFIG2, 59 SMNAND_GPMC_CONFIG3, 60 SMNAND_GPMC_CONFIG4, 61 SMNAND_GPMC_CONFIG5, 62 SMNAND_GPMC_CONFIG6, 63 0, 64 }; 65 66 #ifdef CONFIG_LCD 67 #ifdef CONFIG_CMD_NAND 68 static int splash_load_from_nand(u32 bmp_load_addr) 69 { 70 struct bmp_header *bmp_hdr; 71 int res, splash_screen_nand_offset = 0x100000; 72 size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); 73 74 if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) 75 goto splash_address_too_high; 76 77 res = nand_read_skip_bad(&nand_info[nand_curr_device], 78 splash_screen_nand_offset, &bmp_header_size, 79 NULL, nand_info[nand_curr_device].size, 80 (u_char *)bmp_load_addr); 81 if (res < 0) 82 return res; 83 84 bmp_hdr = (struct bmp_header *)bmp_load_addr; 85 bmp_size = le32_to_cpu(bmp_hdr->file_size); 86 87 if (bmp_load_addr + bmp_size >= gd->start_addr_sp) 88 goto splash_address_too_high; 89 90 return nand_read_skip_bad(&nand_info[nand_curr_device], 91 splash_screen_nand_offset, &bmp_size, 92 NULL, nand_info[nand_curr_device].size, 93 (u_char *)bmp_load_addr); 94 95 splash_address_too_high: 96 printf("Error: splashimage address too high. Data overwrites U-Boot " 97 "and/or placed beyond DRAM boundaries.\n"); 98 99 return -1; 100 } 101 #else 102 static inline int splash_load_from_nand(void) 103 { 104 return -1; 105 } 106 #endif /* CONFIG_CMD_NAND */ 107 108 int splash_screen_prepare(void) 109 { 110 char *env_splashimage_value; 111 u32 bmp_load_addr; 112 113 env_splashimage_value = getenv("splashimage"); 114 if (env_splashimage_value == NULL) 115 return -1; 116 117 bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); 118 if (bmp_load_addr == 0) { 119 printf("Error: bad splashimage address specified\n"); 120 return -1; 121 } 122 123 return splash_load_from_nand(bmp_load_addr); 124 } 125 #endif /* CONFIG_LCD */ 126 127 /* 128 * Routine: board_init 129 * Description: hardware init. 130 */ 131 int board_init(void) 132 { 133 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 134 135 enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0], 136 CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M); 137 138 /* board id for Linux */ 139 if (get_cpu_family() == CPU_OMAP34XX) 140 gd->bd->bi_arch_number = MACH_TYPE_CM_T35; 141 else 142 gd->bd->bi_arch_number = MACH_TYPE_CM_T3730; 143 144 /* boot param addr */ 145 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 146 147 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) 148 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); 149 #endif 150 151 return 0; 152 } 153 154 static u32 cm_t3x_rev; 155 156 /* 157 * Routine: get_board_rev 158 * Description: read system revision 159 */ 160 u32 get_board_rev(void) 161 { 162 if (!cm_t3x_rev) 163 cm_t3x_rev = cm_t3x_eeprom_get_board_rev(); 164 165 return cm_t3x_rev; 166 }; 167 168 /* 169 * Routine: misc_init_r 170 * Description: display die ID 171 */ 172 int misc_init_r(void) 173 { 174 u32 board_rev = get_board_rev(); 175 u32 rev_major = board_rev / 100; 176 u32 rev_minor = board_rev - (rev_major * 100); 177 178 if ((rev_minor / 10) * 10 == rev_minor) 179 rev_minor = rev_minor / 10; 180 181 printf("PCB: %u.%u\n", rev_major, rev_minor); 182 dieid_num_r(); 183 184 return 0; 185 } 186 187 /* 188 * Routine: set_muxconf_regs 189 * Description: Setting up the configuration Mux registers specific to the 190 * hardware. Many pins need to be moved from protect to primary 191 * mode. 192 */ 193 static void cm_t3x_set_common_muxconf(void) 194 { 195 /* SDRC */ 196 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ 197 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ 198 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ 199 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ 200 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ 201 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ 202 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ 203 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ 204 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ 205 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ 206 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ 207 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ 208 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ 209 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ 210 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ 211 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ 212 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ 213 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ 214 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ 215 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ 216 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ 217 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ 218 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ 219 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ 220 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ 221 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ 222 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ 223 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ 224 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ 225 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ 226 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ 227 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ 228 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ 229 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ 230 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ 231 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ 232 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ 233 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ 234 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ 235 236 /* GPMC */ 237 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ 238 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ 239 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ 240 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ 241 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ 242 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ 243 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ 244 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ 245 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ 246 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ 247 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ 248 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ 249 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ 250 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ 251 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ 252 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ 253 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ 254 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ 255 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ 256 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ 257 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ 258 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ 259 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ 260 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ 261 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ 262 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ 263 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ 264 265 /* SB-T35 Ethernet */ 266 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ 267 268 /* DVI enable */ 269 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ 270 271 /* CM-T3x Ethernet */ 272 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ 273 MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ 274 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ 275 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ 276 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/ 277 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ 278 MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/ 279 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/ 280 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ 281 282 /* DSS */ 283 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/ 284 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ 285 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ 286 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ 287 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ 288 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ 289 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ 290 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/ 291 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/ 292 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/ 293 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/ 294 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/ 295 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/ 296 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ 297 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ 298 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ 299 300 /* serial interface */ 301 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ 302 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/ 303 304 /* mUSB */ 305 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ 306 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ 307 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ 308 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ 309 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ 310 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ 311 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ 312 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ 313 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ 314 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ 315 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ 316 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ 317 318 /* USB EHCI */ 319 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ 320 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ 321 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ 322 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ 323 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ 324 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ 325 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ 326 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ 327 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ 328 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ 329 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ 330 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ 331 332 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ 333 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ 334 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ 335 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ 336 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ 337 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ 338 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ 339 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ 340 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ 341 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ 342 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ 343 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ 344 345 /* SB_T35_USB_HUB_RESET_GPIO */ 346 MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ 347 348 /* I2C1 */ 349 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ 350 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ 351 /* I2C2 */ 352 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ 353 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ 354 /* I2C3 */ 355 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ 356 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ 357 358 /* control and debug */ 359 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ 360 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ 361 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ 362 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ 363 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ 364 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/ 365 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/ 366 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ 367 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ 368 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ 369 370 /* MMC1 */ 371 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ 372 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ 373 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ 374 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ 375 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ 376 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ 377 } 378 379 static void cm_t35_set_muxconf(void) 380 { 381 /* DSS */ 382 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ 383 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ 384 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ 385 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ 386 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ 387 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ 388 389 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ 390 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ 391 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ 392 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ 393 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ 394 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ 395 396 /* MMC1 */ 397 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ 398 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ 399 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ 400 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ 401 } 402 403 static void cm_t3730_set_muxconf(void) 404 { 405 /* DSS */ 406 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/ 407 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/ 408 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/ 409 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/ 410 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/ 411 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/ 412 413 MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/ 414 MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/ 415 MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/ 416 MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/ 417 MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/ 418 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/ 419 } 420 421 void set_muxconf_regs(void) 422 { 423 cm_t3x_set_common_muxconf(); 424 425 if (get_cpu_family() == CPU_OMAP34XX) 426 cm_t35_set_muxconf(); 427 else 428 cm_t3730_set_muxconf(); 429 } 430 431 #ifdef CONFIG_GENERIC_MMC 432 int board_mmc_getcd(struct mmc *mmc) 433 { 434 u8 val; 435 436 if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val)) 437 return -1; 438 439 return !(val & 1); 440 } 441 442 int board_mmc_init(bd_t *bis) 443 { 444 return omap_mmc_init(0, 0, 0, -1, 59); 445 } 446 #endif 447 448 /* 449 * Routine: setup_net_chip_gmpc 450 * Description: Setting up the configuration GPMC registers specific to the 451 * Ethernet hardware. 452 */ 453 static void setup_net_chip_gmpc(void) 454 { 455 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 456 457 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], 458 CM_T3X_SMC911X_BASE, GPMC_SIZE_16M); 459 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], 460 SB_T35_SMC911X_BASE, GPMC_SIZE_16M); 461 462 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 463 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 464 465 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 466 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 467 468 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 469 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 470 &ctrl_base->gpmc_nadv_ale); 471 } 472 473 #ifdef CONFIG_DRIVER_OMAP34XX_I2C 474 /* 475 * Routine: reset_net_chip 476 * Description: reset the Ethernet controller via TPS65930 GPIO 477 */ 478 static void reset_net_chip(void) 479 { 480 /* Set GPIO1 of TPS65930 as output */ 481 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, 482 0x02); 483 /* Send a pulse on the GPIO pin */ 484 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 485 0x02); 486 udelay(1); 487 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09, 488 0x02); 489 mdelay(40); 490 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 491 0x02); 492 mdelay(1); 493 } 494 #else 495 static inline void reset_net_chip(void) {} 496 #endif 497 498 #ifdef CONFIG_SMC911X 499 /* 500 * Routine: handle_mac_address 501 * Description: prepare MAC address for on-board Ethernet. 502 */ 503 static int handle_mac_address(void) 504 { 505 unsigned char enetaddr[6]; 506 int rc; 507 508 rc = eth_getenv_enetaddr("ethaddr", enetaddr); 509 if (rc) 510 return 0; 511 512 rc = cm_t3x_eeprom_read_mac_addr(enetaddr); 513 if (rc) 514 return rc; 515 516 if (!is_valid_ether_addr(enetaddr)) 517 return -1; 518 519 return eth_setenv_enetaddr("ethaddr", enetaddr); 520 } 521 522 523 /* 524 * Routine: board_eth_init 525 * Description: initialize module and base-board Ethernet chips 526 */ 527 int board_eth_init(bd_t *bis) 528 { 529 int rc = 0, rc1 = 0; 530 531 setup_net_chip_gmpc(); 532 reset_net_chip(); 533 534 rc1 = handle_mac_address(); 535 if (rc1) 536 printf("No MAC address found! "); 537 538 rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); 539 if (rc1 > 0) 540 rc++; 541 542 rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); 543 if (rc1 > 0) 544 rc++; 545 546 return rc; 547 } 548 #endif 549 550 void __weak get_board_serial(struct tag_serialnr *serialnr) 551 { 552 /* 553 * This corresponds to what happens when we can communicate with the 554 * eeprom but don't get a valid board serial value. 555 */ 556 serialnr->low = 0; 557 serialnr->high = 0; 558 }; 559 560 #ifdef CONFIG_USB_EHCI_OMAP 561 struct omap_usbhs_board_data usbhs_bdata = { 562 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 563 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 564 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 565 }; 566 567 #define SB_T35_USB_HUB_RESET_GPIO 167 568 int ehci_hcd_init(int index, enum usb_init_type init, 569 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 570 { 571 u8 val; 572 int offset; 573 574 if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) { 575 printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset", 576 SB_T35_USB_HUB_RESET_GPIO); 577 return -1; 578 } 579 580 gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0); 581 udelay(10); 582 gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); 583 udelay(1000); 584 585 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; 586 twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); 587 /* Set GPIO6 and GPIO7 of TPS65930 as output */ 588 val |= 0xC0; 589 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val); 590 offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; 591 /* Take both PHYs out of reset */ 592 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0); 593 udelay(1); 594 595 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 596 } 597 598 int ehci_hcd_stop(void) 599 { 600 return omap_ehci_hcd_stop(); 601 } 602 603 #endif /* CONFIG_USB_EHCI_OMAP */ 604