1 /* 2 * SPL specific code for Compulab CM-T335 board 3 * 4 * Board functions for Compulab CM-T335 board 5 * 6 * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ 7 * 8 * Author: Ilya Ledvich <ilya@compulab.co.il> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <errno.h> 15 16 #include <asm/arch/ddr_defs.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/clocks_am33xx.h> 19 #include <asm/arch/sys_proto.h> 20 #include <asm/arch/hardware_am33xx.h> 21 #include <asm/sizes.h> 22 23 static const struct ddr_data ddr3_data = { 24 .datardsratio0 = MT41J128MJT125_RD_DQS, 25 .datawdsratio0 = MT41J128MJT125_WR_DQS, 26 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 27 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 28 }; 29 30 static const struct cmd_control ddr3_cmd_ctrl_data = { 31 .cmd0csratio = MT41J128MJT125_RATIO, 32 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 33 34 .cmd1csratio = MT41J128MJT125_RATIO, 35 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 36 37 .cmd2csratio = MT41J128MJT125_RATIO, 38 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 39 }; 40 41 static struct emif_regs ddr3_emif_reg_data = { 42 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 43 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 44 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 45 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 46 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 47 .zq_config = MT41J128MJT125_ZQ_CFG, 48 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 49 PHY_EN_DYN_PWRDN, 50 }; 51 52 const struct dpll_params dpll_ddr = { 53 /* M N M2 M3 M4 M5 M6 */ 54 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1}; 55 56 void am33xx_spl_board_init(void) 57 { 58 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 59 60 /* Get the frequency */ 61 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 62 63 /* Set CORE Frequencies to OPP100 */ 64 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 65 66 /* Set MPU Frequency to what we detected now that voltages are set */ 67 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 68 } 69 70 const struct dpll_params *get_dpll_ddr_params(void) 71 { 72 return &dpll_ddr; 73 } 74 75 static void probe_sdram_size(long size) 76 { 77 switch (size) { 78 case SZ_512M: 79 ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG; 80 break; 81 case SZ_256M: 82 ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG; 83 break; 84 case SZ_128M: 85 ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG; 86 break; 87 default: 88 puts("Failed configuring DRAM, resetting...\n\n"); 89 reset_cpu(0); 90 } 91 debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); 92 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, 93 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 94 } 95 96 void sdram_init(void) 97 { 98 long size = SZ_1G; 99 100 do { 101 size = size / 2; 102 probe_sdram_size(size); 103 } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size); 104 105 return; 106 } 107