1 /* 2 * SPL specific code for Compulab CM-T335 board 3 * 4 * Board functions for Compulab CM-T335 board 5 * 6 * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ 7 * 8 * Author: Ilya Ledvich <ilya@compulab.co.il> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <errno.h> 15 16 #include <asm/arch/ddr_defs.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/clocks_am33xx.h> 19 #include <asm/arch/sys_proto.h> 20 #include <asm/arch/hardware_am33xx.h> 21 #include <linux/sizes.h> 22 23 const struct ctrl_ioregs ioregs = { 24 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, 25 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, 26 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, 27 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, 28 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, 29 }; 30 31 static const struct ddr_data ddr3_data = { 32 .datardsratio0 = MT41J128MJT125_RD_DQS, 33 .datawdsratio0 = MT41J128MJT125_WR_DQS, 34 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 35 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 36 }; 37 38 static const struct cmd_control ddr3_cmd_ctrl_data = { 39 .cmd0csratio = MT41J128MJT125_RATIO, 40 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 41 42 .cmd1csratio = MT41J128MJT125_RATIO, 43 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 44 45 .cmd2csratio = MT41J128MJT125_RATIO, 46 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 47 }; 48 49 static struct emif_regs ddr3_emif_reg_data = { 50 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 51 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 52 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 53 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 54 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 55 .zq_config = MT41J128MJT125_ZQ_CFG, 56 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 57 PHY_EN_DYN_PWRDN, 58 }; 59 60 const struct dpll_params dpll_ddr = { 61 /* M N M2 M3 M4 M5 M6 */ 62 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1}; 63 64 void am33xx_spl_board_init(void) 65 { 66 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 67 68 /* Get the frequency */ 69 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 70 71 /* Set CORE Frequencies to OPP100 */ 72 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 73 74 /* Set MPU Frequency to what we detected now that voltages are set */ 75 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 76 } 77 78 const struct dpll_params *get_dpll_ddr_params(void) 79 { 80 return &dpll_ddr; 81 } 82 83 static void probe_sdram_size(long size) 84 { 85 switch (size) { 86 case SZ_512M: 87 ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG; 88 break; 89 case SZ_256M: 90 ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG; 91 break; 92 case SZ_128M: 93 ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG; 94 break; 95 default: 96 puts("Failed configuring DRAM, resetting...\n\n"); 97 reset_cpu(0); 98 } 99 debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); 100 config_ddr(303, &ioregs, &ddr3_data, 101 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 102 } 103 104 void sdram_init(void) 105 { 106 long size = SZ_1G; 107 108 do { 109 size = size / 2; 110 probe_sdram_size(size); 111 } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size); 112 113 return; 114 } 115