1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 254e7445dSIlya Ledvich /* 354e7445dSIlya Ledvich * SPL specific code for Compulab CM-T335 board 454e7445dSIlya Ledvich * 554e7445dSIlya Ledvich * Board functions for Compulab CM-T335 board 654e7445dSIlya Ledvich * 754e7445dSIlya Ledvich * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ 854e7445dSIlya Ledvich * 954e7445dSIlya Ledvich * Author: Ilya Ledvich <ilya@compulab.co.il> 1054e7445dSIlya Ledvich */ 1154e7445dSIlya Ledvich 1254e7445dSIlya Ledvich #include <common.h> 1354e7445dSIlya Ledvich #include <errno.h> 1454e7445dSIlya Ledvich 1554e7445dSIlya Ledvich #include <asm/arch/ddr_defs.h> 1654e7445dSIlya Ledvich #include <asm/arch/clock.h> 1754e7445dSIlya Ledvich #include <asm/arch/clocks_am33xx.h> 1854e7445dSIlya Ledvich #include <asm/arch/sys_proto.h> 1954e7445dSIlya Ledvich #include <asm/arch/hardware_am33xx.h> 201ace4022SAlexey Brodkin #include <linux/sizes.h> 2154e7445dSIlya Ledvich 22965de8b9SLokesh Vutla const struct ctrl_ioregs ioregs = { 23965de8b9SLokesh Vutla .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, 24965de8b9SLokesh Vutla .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, 25965de8b9SLokesh Vutla .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, 26965de8b9SLokesh Vutla .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, 27965de8b9SLokesh Vutla .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, 28965de8b9SLokesh Vutla }; 29965de8b9SLokesh Vutla 3054e7445dSIlya Ledvich static const struct ddr_data ddr3_data = { 3154e7445dSIlya Ledvich .datardsratio0 = MT41J128MJT125_RD_DQS, 3254e7445dSIlya Ledvich .datawdsratio0 = MT41J128MJT125_WR_DQS, 3354e7445dSIlya Ledvich .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 3454e7445dSIlya Ledvich .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 3554e7445dSIlya Ledvich }; 3654e7445dSIlya Ledvich 3754e7445dSIlya Ledvich static const struct cmd_control ddr3_cmd_ctrl_data = { 3854e7445dSIlya Ledvich .cmd0csratio = MT41J128MJT125_RATIO, 3954e7445dSIlya Ledvich .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 4054e7445dSIlya Ledvich 4154e7445dSIlya Ledvich .cmd1csratio = MT41J128MJT125_RATIO, 4254e7445dSIlya Ledvich .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 4354e7445dSIlya Ledvich 4454e7445dSIlya Ledvich .cmd2csratio = MT41J128MJT125_RATIO, 4554e7445dSIlya Ledvich .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 4654e7445dSIlya Ledvich }; 4754e7445dSIlya Ledvich 4854e7445dSIlya Ledvich static struct emif_regs ddr3_emif_reg_data = { 4954e7445dSIlya Ledvich .sdram_config = MT41J128MJT125_EMIF_SDCFG, 5054e7445dSIlya Ledvich .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 5154e7445dSIlya Ledvich .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 5254e7445dSIlya Ledvich .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 5354e7445dSIlya Ledvich .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 5454e7445dSIlya Ledvich .zq_config = MT41J128MJT125_ZQ_CFG, 5554e7445dSIlya Ledvich .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 5654e7445dSIlya Ledvich PHY_EN_DYN_PWRDN, 5754e7445dSIlya Ledvich }; 5854e7445dSIlya Ledvich 5954e7445dSIlya Ledvich const struct dpll_params dpll_ddr = { 6054e7445dSIlya Ledvich /* M N M2 M3 M4 M5 M6 */ 6154e7445dSIlya Ledvich 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1}; 6254e7445dSIlya Ledvich 6354e7445dSIlya Ledvich void am33xx_spl_board_init(void) 6454e7445dSIlya Ledvich { 6554e7445dSIlya Ledvich struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 6654e7445dSIlya Ledvich 6754e7445dSIlya Ledvich /* Get the frequency */ 6854e7445dSIlya Ledvich dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 6954e7445dSIlya Ledvich 7054e7445dSIlya Ledvich /* Set CORE Frequencies to OPP100 */ 7154e7445dSIlya Ledvich do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 7254e7445dSIlya Ledvich 7354e7445dSIlya Ledvich /* Set MPU Frequency to what we detected now that voltages are set */ 7454e7445dSIlya Ledvich do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 7554e7445dSIlya Ledvich } 7654e7445dSIlya Ledvich 7754e7445dSIlya Ledvich const struct dpll_params *get_dpll_ddr_params(void) 7854e7445dSIlya Ledvich { 7954e7445dSIlya Ledvich return &dpll_ddr; 8054e7445dSIlya Ledvich } 8154e7445dSIlya Ledvich 8254e7445dSIlya Ledvich static void probe_sdram_size(long size) 8354e7445dSIlya Ledvich { 8454e7445dSIlya Ledvich switch (size) { 8554e7445dSIlya Ledvich case SZ_512M: 8654e7445dSIlya Ledvich ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG; 8754e7445dSIlya Ledvich break; 8854e7445dSIlya Ledvich case SZ_256M: 8954e7445dSIlya Ledvich ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG; 9054e7445dSIlya Ledvich break; 9154e7445dSIlya Ledvich case SZ_128M: 9254e7445dSIlya Ledvich ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG; 9354e7445dSIlya Ledvich break; 9454e7445dSIlya Ledvich default: 9554e7445dSIlya Ledvich puts("Failed configuring DRAM, resetting...\n\n"); 9654e7445dSIlya Ledvich reset_cpu(0); 9754e7445dSIlya Ledvich } 9854e7445dSIlya Ledvich debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20); 99965de8b9SLokesh Vutla config_ddr(303, &ioregs, &ddr3_data, 10054e7445dSIlya Ledvich &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 10154e7445dSIlya Ledvich } 10254e7445dSIlya Ledvich 10354e7445dSIlya Ledvich void sdram_init(void) 10454e7445dSIlya Ledvich { 10554e7445dSIlya Ledvich long size = SZ_1G; 10654e7445dSIlya Ledvich 10754e7445dSIlya Ledvich do { 10854e7445dSIlya Ledvich size = size / 2; 10954e7445dSIlya Ledvich probe_sdram_size(size); 11054e7445dSIlya Ledvich } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size); 11154e7445dSIlya Ledvich 11254e7445dSIlya Ledvich return; 11354e7445dSIlya Ledvich } 114