1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SPL specific code for Compulab CM-FX6 board 4 * 5 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ 6 * 7 * Author: Nikita Kiryanov <nikita@compulab.co.il> 8 */ 9 10 #include <common.h> 11 #include <spl.h> 12 #include <asm/io.h> 13 #include <asm/gpio.h> 14 #include <asm/arch/mx6-ddr.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/crm_regs.h> 18 #include <asm/mach-imx/iomux-v3.h> 19 #include <fsl_esdhc.h> 20 #include "common.h" 21 22 enum ddr_config { 23 DDR_16BIT_256MB, 24 DDR_32BIT_512MB, 25 DDR_32BIT_1GB, 26 DDR_64BIT_1GB, 27 DDR_64BIT_2GB, 28 DDR_64BIT_4GB, 29 DDR_UNKNOWN, 30 }; 31 32 /* 33 * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to 34 * Freescale QRM, but this is exactly the value used by the automatic 35 * calibration script and it works also in all our tests, so we leave 36 * it as is at this point. 37 */ 38 #define CM_FX6_DDR_IOMUX_CFG \ 39 .dram_sdqs0 = 0x00000038, \ 40 .dram_sdqs1 = 0x00000038, \ 41 .dram_sdqs2 = 0x00000038, \ 42 .dram_sdqs3 = 0x00000038, \ 43 .dram_sdqs4 = 0x00000038, \ 44 .dram_sdqs5 = 0x00000038, \ 45 .dram_sdqs6 = 0x00000038, \ 46 .dram_sdqs7 = 0x00000038, \ 47 .dram_dqm0 = 0x00000038, \ 48 .dram_dqm1 = 0x00000038, \ 49 .dram_dqm2 = 0x00000038, \ 50 .dram_dqm3 = 0x00000038, \ 51 .dram_dqm4 = 0x00000038, \ 52 .dram_dqm5 = 0x00000038, \ 53 .dram_dqm6 = 0x00000038, \ 54 .dram_dqm7 = 0x00000038, \ 55 .dram_cas = 0x00000038, \ 56 .dram_ras = 0x00000038, \ 57 .dram_sdclk_0 = 0x00000038, \ 58 .dram_sdclk_1 = 0x00000038, \ 59 .dram_sdcke0 = 0x00003000, \ 60 .dram_sdcke1 = 0x00003000, \ 61 .dram_reset = 0x00000038, \ 62 .dram_sdba2 = 0x00000000, \ 63 .dram_sdodt0 = 0x00000038, \ 64 .dram_sdodt1 = 0x00000038, 65 66 #define CM_FX6_GPR_IOMUX_CFG \ 67 .grp_b0ds = 0x00000038, \ 68 .grp_b1ds = 0x00000038, \ 69 .grp_b2ds = 0x00000038, \ 70 .grp_b3ds = 0x00000038, \ 71 .grp_b4ds = 0x00000038, \ 72 .grp_b5ds = 0x00000038, \ 73 .grp_b6ds = 0x00000038, \ 74 .grp_b7ds = 0x00000038, \ 75 .grp_addds = 0x00000038, \ 76 .grp_ddrmode_ctl = 0x00020000, \ 77 .grp_ddrpke = 0x00000000, \ 78 .grp_ddrmode = 0x00020000, \ 79 .grp_ctlds = 0x00000038, \ 80 .grp_ddr_type = 0x000C0000, 81 82 static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG }; 83 static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG }; 84 static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG }; 85 static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG }; 86 87 static struct mx6_mmdc_calibration cm_fx6_calib_s = { 88 .p0_mpwldectrl0 = 0x005B0061, 89 .p0_mpwldectrl1 = 0x004F0055, 90 .p0_mpdgctrl0 = 0x0314030C, 91 .p0_mpdgctrl1 = 0x025C0268, 92 .p0_mprddlctl = 0x42464646, 93 .p0_mpwrdlctl = 0x36322C34, 94 }; 95 96 static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = { 97 .cs1_mirror = 1, 98 .cs_density = 16, 99 .bi_on = 1, 100 .rtt_nom = 1, 101 .rtt_wr = 0, 102 .ralat = 5, 103 .walat = 1, 104 .mif3_mode = 3, 105 .rst_to_cke = 0x23, 106 .sde_to_rst = 0x10, 107 }; 108 109 static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = { 110 .mem_speed = 800, 111 .density = 4, 112 .rowaddr = 14, 113 .coladdr = 10, 114 .pagesz = 2, 115 .trcd = 1800, 116 .trcmin = 5200, 117 .trasmin = 3600, 118 .SRT = 0, 119 }; 120 121 static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset) 122 { 123 if (reset) 124 ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; 125 126 switch (dram_config) { 127 case DDR_16BIT_256MB: 128 cm_fx6_sysinfo_s.dsize = 0; 129 cm_fx6_sysinfo_s.ncs = 1; 130 break; 131 case DDR_32BIT_512MB: 132 cm_fx6_sysinfo_s.dsize = 1; 133 cm_fx6_sysinfo_s.ncs = 1; 134 break; 135 case DDR_32BIT_1GB: 136 cm_fx6_sysinfo_s.dsize = 1; 137 cm_fx6_sysinfo_s.ncs = 2; 138 break; 139 default: 140 puts("Tried to setup invalid DDR configuration\n"); 141 hang(); 142 } 143 144 mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s); 145 udelay(100); 146 } 147 148 static struct mx6_mmdc_calibration cm_fx6_calib_q = { 149 .p0_mpwldectrl0 = 0x00630068, 150 .p0_mpwldectrl1 = 0x0068005D, 151 .p0_mpdgctrl0 = 0x04140428, 152 .p0_mpdgctrl1 = 0x037C037C, 153 .p0_mprddlctl = 0x3C30303A, 154 .p0_mpwrdlctl = 0x3A344038, 155 .p1_mpwldectrl0 = 0x0035004C, 156 .p1_mpwldectrl1 = 0x00170026, 157 .p1_mpdgctrl0 = 0x0374037C, 158 .p1_mpdgctrl1 = 0x0350032C, 159 .p1_mprddlctl = 0x30322A3C, 160 .p1_mpwrdlctl = 0x48304A3E, 161 }; 162 163 static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = { 164 .cs_density = 16, 165 .cs1_mirror = 1, 166 .bi_on = 1, 167 .rtt_nom = 1, 168 .rtt_wr = 0, 169 .ralat = 5, 170 .walat = 1, 171 .mif3_mode = 3, 172 .rst_to_cke = 0x23, 173 .sde_to_rst = 0x10, 174 .refsel = 1, /* Refresh cycles at 32KHz */ 175 .refr = 7, /* 8 refresh commands per refresh cycle */ 176 }; 177 178 static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = { 179 .mem_speed = 1066, 180 .density = 4, 181 .rowaddr = 14, 182 .coladdr = 10, 183 .pagesz = 2, 184 .trcd = 1324, 185 .trcmin = 59500, 186 .trasmin = 9750, 187 .SRT = 0, 188 }; 189 190 static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset) 191 { 192 if (reset) 193 ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; 194 195 cm_fx6_ddr3_cfg_q.rowaddr = 14; 196 switch (dram_config) { 197 case DDR_16BIT_256MB: 198 cm_fx6_sysinfo_q.dsize = 0; 199 cm_fx6_sysinfo_q.ncs = 1; 200 break; 201 case DDR_32BIT_512MB: 202 cm_fx6_sysinfo_q.dsize = 1; 203 cm_fx6_sysinfo_q.ncs = 1; 204 break; 205 case DDR_64BIT_1GB: 206 cm_fx6_sysinfo_q.dsize = 2; 207 cm_fx6_sysinfo_q.ncs = 1; 208 break; 209 case DDR_64BIT_2GB: 210 cm_fx6_sysinfo_q.dsize = 2; 211 cm_fx6_sysinfo_q.ncs = 2; 212 break; 213 case DDR_64BIT_4GB: 214 cm_fx6_sysinfo_q.dsize = 2; 215 cm_fx6_sysinfo_q.ncs = 2; 216 cm_fx6_ddr3_cfg_q.rowaddr = 15; 217 break; 218 default: 219 puts("Tried to setup invalid DDR configuration\n"); 220 hang(); 221 } 222 223 mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q); 224 udelay(100); 225 } 226 227 static int cm_fx6_spl_dram_init(void) 228 { 229 unsigned long bank1_size, bank2_size; 230 231 switch (get_cpu_type()) { 232 case MXC_CPU_MX6SOLO: 233 mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s); 234 235 spl_mx6s_dram_init(DDR_32BIT_1GB, false); 236 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); 237 bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000); 238 if (bank1_size == 0x20000000) { 239 if (bank2_size == 0x20000000) 240 return 0; 241 242 spl_mx6s_dram_init(DDR_32BIT_512MB, true); 243 return 0; 244 } 245 246 spl_mx6s_dram_init(DDR_16BIT_256MB, true); 247 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); 248 if (bank1_size == 0x10000000) 249 return 0; 250 251 break; 252 case MXC_CPU_MX6D: 253 case MXC_CPU_MX6Q: 254 mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q); 255 256 spl_mx6q_dram_init(DDR_64BIT_4GB, false); 257 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); 258 if (bank1_size == 0x80000000) 259 return 0; 260 261 if (bank1_size == 0x40000000) { 262 bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 263 0x80000000); 264 if (bank2_size == 0x40000000) { 265 /* Don't do a full reset here */ 266 spl_mx6q_dram_init(DDR_64BIT_2GB, false); 267 } else { 268 spl_mx6q_dram_init(DDR_64BIT_1GB, true); 269 } 270 271 return 0; 272 } 273 274 spl_mx6q_dram_init(DDR_32BIT_512MB, true); 275 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); 276 if (bank1_size == 0x20000000) 277 return 0; 278 279 spl_mx6q_dram_init(DDR_16BIT_256MB, true); 280 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); 281 if (bank1_size == 0x10000000) 282 return 0; 283 284 break; 285 } 286 287 return -1; 288 } 289 290 static iomux_v3_cfg_t const uart4_pads[] = { 291 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 292 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 293 }; 294 295 static void cm_fx6_setup_uart(void) 296 { 297 SETUP_IOMUX_PADS(uart4_pads); 298 enable_uart_clk(1); 299 } 300 301 #ifdef CONFIG_SPL_SPI_SUPPORT 302 static void cm_fx6_setup_ecspi(void) 303 { 304 cm_fx6_set_ecspi_iomux(); 305 enable_spi_clk(1, 0); 306 } 307 #else 308 static void cm_fx6_setup_ecspi(void) { } 309 #endif 310 311 void board_init_f(ulong dummy) 312 { 313 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 314 315 /* 316 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot 317 * initializes DMA very early (before all board code), so the only 318 * opportunity we have to initialize APBHDMA clocks is in SPL. 319 */ 320 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 321 enable_usdhc_clk(1, 2); 322 323 arch_cpu_init(); 324 timer_init(); 325 cm_fx6_setup_ecspi(); 326 cm_fx6_setup_uart(); 327 get_clocks(); 328 preloader_console_init(); 329 gpio_direction_output(CM_FX6_GREEN_LED, 1); 330 if (cm_fx6_spl_dram_init()) { 331 puts("!!!ERROR!!! DRAM detection failed!!!\n"); 332 hang(); 333 } 334 } 335 336 void board_boot_order(u32 *spl_boot_list) 337 { 338 spl_boot_list[0] = spl_boot_device(); 339 switch (spl_boot_list[0]) { 340 case BOOT_DEVICE_SPI: 341 spl_boot_list[1] = BOOT_DEVICE_MMC1; 342 break; 343 case BOOT_DEVICE_MMC1: 344 spl_boot_list[1] = BOOT_DEVICE_SPI; 345 break; 346 } 347 } 348 349 #ifdef CONFIG_SPL_MMC_SUPPORT 350 static struct fsl_esdhc_cfg usdhc_cfg = { 351 .esdhc_base = USDHC3_BASE_ADDR, 352 .max_bus_width = 4, 353 }; 354 355 int board_mmc_init(bd_t *bis) 356 { 357 cm_fx6_set_usdhc_iomux(); 358 359 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 360 361 return fsl_esdhc_initialize(bis, &usdhc_cfg); 362 } 363 #endif 364