1 /* 2 * SPL specific code for Compulab CM-FX6 board 3 * 4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ 5 * 6 * Author: Nikita Kiryanov <nikita@compulab.co.il> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <spl.h> 13 #include <asm/io.h> 14 #include <asm/gpio.h> 15 #include <asm/arch/mx6-ddr.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/sys_proto.h> 18 #include <asm/arch/crm_regs.h> 19 #include <asm/mach-imx/iomux-v3.h> 20 #include <fsl_esdhc.h> 21 #include "common.h" 22 23 enum ddr_config { 24 DDR_16BIT_256MB, 25 DDR_32BIT_512MB, 26 DDR_32BIT_1GB, 27 DDR_64BIT_1GB, 28 DDR_64BIT_2GB, 29 DDR_64BIT_4GB, 30 DDR_UNKNOWN, 31 }; 32 33 /* 34 * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to 35 * Freescale QRM, but this is exactly the value used by the automatic 36 * calibration script and it works also in all our tests, so we leave 37 * it as is at this point. 38 */ 39 #define CM_FX6_DDR_IOMUX_CFG \ 40 .dram_sdqs0 = 0x00000038, \ 41 .dram_sdqs1 = 0x00000038, \ 42 .dram_sdqs2 = 0x00000038, \ 43 .dram_sdqs3 = 0x00000038, \ 44 .dram_sdqs4 = 0x00000038, \ 45 .dram_sdqs5 = 0x00000038, \ 46 .dram_sdqs6 = 0x00000038, \ 47 .dram_sdqs7 = 0x00000038, \ 48 .dram_dqm0 = 0x00000038, \ 49 .dram_dqm1 = 0x00000038, \ 50 .dram_dqm2 = 0x00000038, \ 51 .dram_dqm3 = 0x00000038, \ 52 .dram_dqm4 = 0x00000038, \ 53 .dram_dqm5 = 0x00000038, \ 54 .dram_dqm6 = 0x00000038, \ 55 .dram_dqm7 = 0x00000038, \ 56 .dram_cas = 0x00000038, \ 57 .dram_ras = 0x00000038, \ 58 .dram_sdclk_0 = 0x00000038, \ 59 .dram_sdclk_1 = 0x00000038, \ 60 .dram_sdcke0 = 0x00003000, \ 61 .dram_sdcke1 = 0x00003000, \ 62 .dram_reset = 0x00000038, \ 63 .dram_sdba2 = 0x00000000, \ 64 .dram_sdodt0 = 0x00000038, \ 65 .dram_sdodt1 = 0x00000038, 66 67 #define CM_FX6_GPR_IOMUX_CFG \ 68 .grp_b0ds = 0x00000038, \ 69 .grp_b1ds = 0x00000038, \ 70 .grp_b2ds = 0x00000038, \ 71 .grp_b3ds = 0x00000038, \ 72 .grp_b4ds = 0x00000038, \ 73 .grp_b5ds = 0x00000038, \ 74 .grp_b6ds = 0x00000038, \ 75 .grp_b7ds = 0x00000038, \ 76 .grp_addds = 0x00000038, \ 77 .grp_ddrmode_ctl = 0x00020000, \ 78 .grp_ddrpke = 0x00000000, \ 79 .grp_ddrmode = 0x00020000, \ 80 .grp_ctlds = 0x00000038, \ 81 .grp_ddr_type = 0x000C0000, 82 83 static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG }; 84 static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG }; 85 static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG }; 86 static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG }; 87 88 static struct mx6_mmdc_calibration cm_fx6_calib_s = { 89 .p0_mpwldectrl0 = 0x005B0061, 90 .p0_mpwldectrl1 = 0x004F0055, 91 .p0_mpdgctrl0 = 0x0314030C, 92 .p0_mpdgctrl1 = 0x025C0268, 93 .p0_mprddlctl = 0x42464646, 94 .p0_mpwrdlctl = 0x36322C34, 95 }; 96 97 static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = { 98 .cs1_mirror = 1, 99 .cs_density = 16, 100 .bi_on = 1, 101 .rtt_nom = 1, 102 .rtt_wr = 0, 103 .ralat = 5, 104 .walat = 1, 105 .mif3_mode = 3, 106 .rst_to_cke = 0x23, 107 .sde_to_rst = 0x10, 108 }; 109 110 static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = { 111 .mem_speed = 800, 112 .density = 4, 113 .rowaddr = 14, 114 .coladdr = 10, 115 .pagesz = 2, 116 .trcd = 1800, 117 .trcmin = 5200, 118 .trasmin = 3600, 119 .SRT = 0, 120 }; 121 122 static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset) 123 { 124 if (reset) 125 ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; 126 127 switch (dram_config) { 128 case DDR_16BIT_256MB: 129 cm_fx6_sysinfo_s.dsize = 0; 130 cm_fx6_sysinfo_s.ncs = 1; 131 break; 132 case DDR_32BIT_512MB: 133 cm_fx6_sysinfo_s.dsize = 1; 134 cm_fx6_sysinfo_s.ncs = 1; 135 break; 136 case DDR_32BIT_1GB: 137 cm_fx6_sysinfo_s.dsize = 1; 138 cm_fx6_sysinfo_s.ncs = 2; 139 break; 140 default: 141 puts("Tried to setup invalid DDR configuration\n"); 142 hang(); 143 } 144 145 mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s); 146 udelay(100); 147 } 148 149 static struct mx6_mmdc_calibration cm_fx6_calib_q = { 150 .p0_mpwldectrl0 = 0x00630068, 151 .p0_mpwldectrl1 = 0x0068005D, 152 .p0_mpdgctrl0 = 0x04140428, 153 .p0_mpdgctrl1 = 0x037C037C, 154 .p0_mprddlctl = 0x3C30303A, 155 .p0_mpwrdlctl = 0x3A344038, 156 .p1_mpwldectrl0 = 0x0035004C, 157 .p1_mpwldectrl1 = 0x00170026, 158 .p1_mpdgctrl0 = 0x0374037C, 159 .p1_mpdgctrl1 = 0x0350032C, 160 .p1_mprddlctl = 0x30322A3C, 161 .p1_mpwrdlctl = 0x48304A3E, 162 }; 163 164 static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = { 165 .cs_density = 16, 166 .cs1_mirror = 1, 167 .bi_on = 1, 168 .rtt_nom = 1, 169 .rtt_wr = 0, 170 .ralat = 5, 171 .walat = 1, 172 .mif3_mode = 3, 173 .rst_to_cke = 0x23, 174 .sde_to_rst = 0x10, 175 .refsel = 1, /* Refresh cycles at 32KHz */ 176 .refr = 7, /* 8 refresh commands per refresh cycle */ 177 }; 178 179 static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = { 180 .mem_speed = 1066, 181 .density = 4, 182 .rowaddr = 14, 183 .coladdr = 10, 184 .pagesz = 2, 185 .trcd = 1324, 186 .trcmin = 59500, 187 .trasmin = 9750, 188 .SRT = 0, 189 }; 190 191 static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset) 192 { 193 if (reset) 194 ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; 195 196 cm_fx6_ddr3_cfg_q.rowaddr = 14; 197 switch (dram_config) { 198 case DDR_16BIT_256MB: 199 cm_fx6_sysinfo_q.dsize = 0; 200 cm_fx6_sysinfo_q.ncs = 1; 201 break; 202 case DDR_32BIT_512MB: 203 cm_fx6_sysinfo_q.dsize = 1; 204 cm_fx6_sysinfo_q.ncs = 1; 205 break; 206 case DDR_64BIT_1GB: 207 cm_fx6_sysinfo_q.dsize = 2; 208 cm_fx6_sysinfo_q.ncs = 1; 209 break; 210 case DDR_64BIT_2GB: 211 cm_fx6_sysinfo_q.dsize = 2; 212 cm_fx6_sysinfo_q.ncs = 2; 213 break; 214 case DDR_64BIT_4GB: 215 cm_fx6_sysinfo_q.dsize = 2; 216 cm_fx6_sysinfo_q.ncs = 2; 217 cm_fx6_ddr3_cfg_q.rowaddr = 15; 218 break; 219 default: 220 puts("Tried to setup invalid DDR configuration\n"); 221 hang(); 222 } 223 224 mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q); 225 udelay(100); 226 } 227 228 static int cm_fx6_spl_dram_init(void) 229 { 230 unsigned long bank1_size, bank2_size; 231 232 switch (get_cpu_type()) { 233 case MXC_CPU_MX6SOLO: 234 mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s); 235 236 spl_mx6s_dram_init(DDR_32BIT_1GB, false); 237 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); 238 bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000); 239 if (bank1_size == 0x20000000) { 240 if (bank2_size == 0x20000000) 241 return 0; 242 243 spl_mx6s_dram_init(DDR_32BIT_512MB, true); 244 return 0; 245 } 246 247 spl_mx6s_dram_init(DDR_16BIT_256MB, true); 248 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); 249 if (bank1_size == 0x10000000) 250 return 0; 251 252 break; 253 case MXC_CPU_MX6D: 254 case MXC_CPU_MX6Q: 255 mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q); 256 257 spl_mx6q_dram_init(DDR_64BIT_4GB, false); 258 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); 259 if (bank1_size == 0x80000000) 260 return 0; 261 262 if (bank1_size == 0x40000000) { 263 bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 264 0x80000000); 265 if (bank2_size == 0x40000000) { 266 /* Don't do a full reset here */ 267 spl_mx6q_dram_init(DDR_64BIT_2GB, false); 268 } else { 269 spl_mx6q_dram_init(DDR_64BIT_1GB, true); 270 } 271 272 return 0; 273 } 274 275 spl_mx6q_dram_init(DDR_32BIT_512MB, true); 276 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); 277 if (bank1_size == 0x20000000) 278 return 0; 279 280 spl_mx6q_dram_init(DDR_16BIT_256MB, true); 281 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000); 282 if (bank1_size == 0x10000000) 283 return 0; 284 285 break; 286 } 287 288 return -1; 289 } 290 291 static iomux_v3_cfg_t const uart4_pads[] = { 292 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 293 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 294 }; 295 296 static void cm_fx6_setup_uart(void) 297 { 298 SETUP_IOMUX_PADS(uart4_pads); 299 enable_uart_clk(1); 300 } 301 302 #ifdef CONFIG_SPL_SPI_SUPPORT 303 static void cm_fx6_setup_ecspi(void) 304 { 305 cm_fx6_set_ecspi_iomux(); 306 enable_spi_clk(1, 0); 307 } 308 #else 309 static void cm_fx6_setup_ecspi(void) { } 310 #endif 311 312 void board_init_f(ulong dummy) 313 { 314 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 315 316 /* 317 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot 318 * initializes DMA very early (before all board code), so the only 319 * opportunity we have to initialize APBHDMA clocks is in SPL. 320 */ 321 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 322 enable_usdhc_clk(1, 2); 323 324 arch_cpu_init(); 325 timer_init(); 326 cm_fx6_setup_ecspi(); 327 cm_fx6_setup_uart(); 328 get_clocks(); 329 preloader_console_init(); 330 gpio_direction_output(CM_FX6_GREEN_LED, 1); 331 if (cm_fx6_spl_dram_init()) { 332 puts("!!!ERROR!!! DRAM detection failed!!!\n"); 333 hang(); 334 } 335 } 336 337 void board_boot_order(u32 *spl_boot_list) 338 { 339 spl_boot_list[0] = spl_boot_device(); 340 switch (spl_boot_list[0]) { 341 case BOOT_DEVICE_SPI: 342 spl_boot_list[1] = BOOT_DEVICE_MMC1; 343 break; 344 case BOOT_DEVICE_MMC1: 345 spl_boot_list[1] = BOOT_DEVICE_SPI; 346 break; 347 } 348 } 349 350 #ifdef CONFIG_SPL_MMC_SUPPORT 351 static struct fsl_esdhc_cfg usdhc_cfg = { 352 .esdhc_base = USDHC3_BASE_ADDR, 353 .max_bus_width = 4, 354 }; 355 356 int board_mmc_init(bd_t *bis) 357 { 358 cm_fx6_set_usdhc_iomux(); 359 360 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 361 362 return fsl_esdhc_initialize(bis, &usdhc_cfg); 363 } 364 #endif 365