1 /* 2 * Board functions for Compulab CM-FX6 board 3 * 4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ 5 * 6 * Author: Nikita Kiryanov <nikita@compulab.co.il> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <fsl_esdhc.h> 14 #include <miiphy.h> 15 #include <netdev.h> 16 #include <fdt_support.h> 17 #include <sata.h> 18 #include <asm/arch/crm_regs.h> 19 #include <asm/arch/sys_proto.h> 20 #include <asm/arch/iomux.h> 21 #include <asm/imx-common/mxc_i2c.h> 22 #include <asm/imx-common/sata.h> 23 #include <asm/io.h> 24 #include <asm/gpio.h> 25 #include <dm/platform_data/serial_mxc.h> 26 #include "common.h" 27 #include "../common/eeprom.h" 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #ifdef CONFIG_DWC_AHSATA 32 static int cm_fx6_issd_gpios[] = { 33 /* The order of the GPIOs in the array is important! */ 34 CM_FX6_SATA_PHY_SLP, 35 CM_FX6_SATA_NRSTDLY, 36 CM_FX6_SATA_PWREN, 37 CM_FX6_SATA_NSTANDBY1, 38 CM_FX6_SATA_NSTANDBY2, 39 CM_FX6_SATA_LDO_EN, 40 }; 41 42 static void cm_fx6_sata_power(int on) 43 { 44 int i; 45 46 if (!on) { /* tell the iSSD that the power will be removed */ 47 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1); 48 mdelay(10); 49 } 50 51 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { 52 gpio_direction_output(cm_fx6_issd_gpios[i], on); 53 udelay(100); 54 } 55 56 if (!on) /* for compatibility lower the power loss interrupt */ 57 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); 58 } 59 60 static iomux_v3_cfg_t const sata_pads[] = { 61 /* SATA PWR */ 62 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), 63 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), 64 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), 65 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 66 /* SATA CTRL */ 67 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), 68 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)), 69 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), 70 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 71 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), 72 }; 73 74 static int cm_fx6_setup_issd(void) 75 { 76 int ret, i; 77 78 SETUP_IOMUX_PADS(sata_pads); 79 80 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { 81 ret = gpio_request(cm_fx6_issd_gpios[i], "sata"); 82 if (ret) 83 return ret; 84 } 85 86 ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int"); 87 if (ret) 88 return ret; 89 90 return 0; 91 } 92 93 #define CM_FX6_SATA_INIT_RETRIES 10 94 int sata_initialize(void) 95 { 96 int err, i; 97 98 /* Make sure this gpio has logical 0 value */ 99 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); 100 udelay(100); 101 102 cm_fx6_sata_power(0); 103 mdelay(250); 104 cm_fx6_sata_power(1); 105 106 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) { 107 err = setup_sata(); 108 if (err) { 109 printf("SATA setup failed: %d\n", err); 110 return err; 111 } 112 113 udelay(100); 114 115 err = __sata_initialize(); 116 if (!err) 117 break; 118 119 /* There is no device on the SATA port */ 120 if (sata_port_status(0, 0) == 0) 121 break; 122 123 /* There's a device, but link not established. Retry */ 124 } 125 126 return err; 127 } 128 #else 129 static int cm_fx6_setup_issd(void) { return 0; } 130 #endif 131 132 #ifdef CONFIG_SYS_I2C_MXC 133 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 134 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 135 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 136 137 I2C_PADS(i2c0_pads, 138 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), 139 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL), 140 IMX_GPIO_NR(3, 21), 141 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), 142 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL), 143 IMX_GPIO_NR(3, 28)); 144 145 I2C_PADS(i2c1_pads, 146 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), 147 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), 148 IMX_GPIO_NR(4, 12), 149 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), 150 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), 151 IMX_GPIO_NR(4, 13)); 152 153 I2C_PADS(i2c2_pads, 154 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), 155 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL), 156 IMX_GPIO_NR(1, 3), 157 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), 158 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL), 159 IMX_GPIO_NR(1, 6)); 160 161 162 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads) 163 { 164 int ret; 165 166 ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads); 167 if (ret) 168 printf("Warning: I2C%d setup failed: %d\n", busnum, ret); 169 170 return ret; 171 } 172 173 static int cm_fx6_setup_i2c(void) 174 { 175 int ret = 0, err; 176 177 /* i2c<x>_pads are wierd macro variables; we can't use an array */ 178 err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads)); 179 if (err) 180 ret = err; 181 err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads)); 182 if (err) 183 ret = err; 184 err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads)); 185 if (err) 186 ret = err; 187 188 return ret; 189 } 190 #else 191 static int cm_fx6_setup_i2c(void) { return 0; } 192 #endif 193 194 #ifdef CONFIG_USB_EHCI_MX6 195 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ 196 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 197 PAD_CTL_HYS | PAD_CTL_SRE_SLOW) 198 #define MX6_USBNC_BASEADDR 0x2184800 199 #define USBNC_USB_H1_PWR_POL (1 << 9) 200 201 static int cm_fx6_setup_usb_host(void) 202 { 203 int err; 204 205 err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst"); 206 if (err) 207 return err; 208 209 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)); 210 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)); 211 212 return 0; 213 } 214 215 static int cm_fx6_setup_usb_otg(void) 216 { 217 int err; 218 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 219 220 err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr"); 221 if (err) { 222 printf("USB OTG pwr gpio request failed: %d\n", err); 223 return err; 224 } 225 226 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL)); 227 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID | 228 MUX_PAD_CTRL(WEAK_PULLDOWN)); 229 clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK); 230 /* disable ext. charger detect, or it'll affect signal quality at dp. */ 231 return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0); 232 } 233 234 int board_ehci_hcd_init(int port) 235 { 236 int ret; 237 u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4); 238 239 /* Only 1 host controller in use. port 0 is OTG & needs no attention */ 240 if (port != 1) 241 return 0; 242 243 /* Set PWR polarity to match power switch's enable polarity */ 244 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL); 245 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0); 246 if (ret) 247 return ret; 248 249 udelay(10); 250 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1); 251 if (ret) 252 return ret; 253 254 mdelay(1); 255 256 return 0; 257 } 258 259 int board_ehci_power(int port, int on) 260 { 261 if (port == 0) 262 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on); 263 264 return 0; 265 } 266 #else 267 static int cm_fx6_setup_usb_otg(void) { return 0; } 268 static int cm_fx6_setup_usb_host(void) { return 0; } 269 #endif 270 271 #ifdef CONFIG_FEC_MXC 272 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 273 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 274 275 static int mx6_rgmii_rework(struct phy_device *phydev) 276 { 277 unsigned short val; 278 279 /* Ar8031 phy SmartEEE feature cause link status generates glitch, 280 * which cause ethernet link down/up issue, so disable SmartEEE 281 */ 282 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); 283 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); 284 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); 285 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 286 val &= ~(0x1 << 8); 287 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 288 289 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 290 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 291 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 292 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 293 294 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 295 val &= 0xffe3; 296 val |= 0x18; 297 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 298 299 /* introduce tx clock delay */ 300 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 301 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 302 val |= 0x0100; 303 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 304 305 return 0; 306 } 307 308 int board_phy_config(struct phy_device *phydev) 309 { 310 mx6_rgmii_rework(phydev); 311 312 if (phydev->drv->config) 313 return phydev->drv->config(phydev); 314 315 return 0; 316 } 317 318 static iomux_v3_cfg_t const enet_pads[] = { 319 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 320 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 321 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 322 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 323 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 324 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 325 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 326 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 327 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 328 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 329 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 330 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 331 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)), 332 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)), 333 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)), 334 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | 335 MUX_PAD_CTRL(ENET_PAD_CTRL)), 336 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | 337 MUX_PAD_CTRL(ENET_PAD_CTRL)), 338 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | 339 MUX_PAD_CTRL(ENET_PAD_CTRL)), 340 }; 341 342 static int handle_mac_address(void) 343 { 344 unsigned char enetaddr[6]; 345 int rc; 346 347 rc = eth_getenv_enetaddr("ethaddr", enetaddr); 348 if (rc) 349 return 0; 350 351 rc = cl_eeprom_read_mac_addr(enetaddr); 352 if (rc) 353 return rc; 354 355 if (!is_valid_ether_addr(enetaddr)) 356 return -1; 357 358 return eth_setenv_enetaddr("ethaddr", enetaddr); 359 } 360 361 int board_eth_init(bd_t *bis) 362 { 363 int err; 364 365 err = handle_mac_address(); 366 if (err) 367 puts("No MAC address found\n"); 368 369 SETUP_IOMUX_PADS(enet_pads); 370 /* phy reset */ 371 err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst"); 372 if (err) 373 printf("Etnernet NRST gpio request failed: %d\n", err); 374 gpio_direction_output(CM_FX6_ENET_NRST, 0); 375 udelay(500); 376 gpio_set_value(CM_FX6_ENET_NRST, 1); 377 enable_enet_clk(1); 378 return cpu_eth_init(bis); 379 } 380 #endif 381 382 #ifdef CONFIG_NAND_MXS 383 static iomux_v3_cfg_t const nand_pads[] = { 384 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), 385 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), 386 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 387 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 388 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), 389 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), 390 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 391 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), 392 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), 393 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), 394 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 395 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), 396 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 397 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 398 }; 399 400 static void cm_fx6_setup_gpmi_nand(void) 401 { 402 SETUP_IOMUX_PADS(nand_pads); 403 /* Enable clock roots */ 404 enable_usdhc_clk(1, 3); 405 enable_usdhc_clk(1, 4); 406 407 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) | 408 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) | 409 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0)); 410 } 411 #else 412 static void cm_fx6_setup_gpmi_nand(void) {} 413 #endif 414 415 #ifdef CONFIG_FSL_ESDHC 416 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 417 {USDHC1_BASE_ADDR}, 418 {USDHC2_BASE_ADDR}, 419 {USDHC3_BASE_ADDR}, 420 }; 421 422 static enum mxc_clock usdhc_clk[3] = { 423 MXC_ESDHC_CLK, 424 MXC_ESDHC2_CLK, 425 MXC_ESDHC3_CLK, 426 }; 427 428 int board_mmc_init(bd_t *bis) 429 { 430 int i; 431 432 cm_fx6_set_usdhc_iomux(); 433 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 434 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]); 435 usdhc_cfg[i].max_bus_width = 4; 436 fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 437 enable_usdhc_clk(1, i); 438 } 439 440 return 0; 441 } 442 #endif 443 444 #ifdef CONFIG_MXC_SPI 445 int cm_fx6_setup_ecspi(void) 446 { 447 cm_fx6_set_ecspi_iomux(); 448 return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0"); 449 } 450 #else 451 int cm_fx6_setup_ecspi(void) { return 0; } 452 #endif 453 454 #ifdef CONFIG_OF_BOARD_SETUP 455 void ft_board_setup(void *blob, bd_t *bd) 456 { 457 uint8_t enetaddr[6]; 458 459 /* MAC addr */ 460 if (eth_getenv_enetaddr("ethaddr", enetaddr)) { 461 fdt_find_and_setprop(blob, "/fec", "local-mac-address", 462 enetaddr, 6, 1); 463 } 464 } 465 #endif 466 467 int board_init(void) 468 { 469 int ret; 470 471 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 472 cm_fx6_setup_gpmi_nand(); 473 474 ret = cm_fx6_setup_ecspi(); 475 if (ret) 476 printf("Warning: ECSPI setup failed: %d\n", ret); 477 478 ret = cm_fx6_setup_usb_otg(); 479 if (ret) 480 printf("Warning: USB OTG setup failed: %d\n", ret); 481 482 ret = cm_fx6_setup_usb_host(); 483 if (ret) 484 printf("Warning: USB host setup failed: %d\n", ret); 485 486 /* 487 * cm-fx6 may have iSSD not assembled and in this case it has 488 * bypasses for a (m)SATA socket on the baseboard. The socketed 489 * device is not controlled by those GPIOs. So just print a warning 490 * if the setup fails. 491 */ 492 ret = cm_fx6_setup_issd(); 493 if (ret) 494 printf("Warning: iSSD setup failed: %d\n", ret); 495 496 /* Warn on failure but do not abort boot */ 497 ret = cm_fx6_setup_i2c(); 498 if (ret) 499 printf("Warning: I2C setup failed: %d\n", ret); 500 501 return 0; 502 } 503 504 int checkboard(void) 505 { 506 puts("Board: CM-FX6\n"); 507 return 0; 508 } 509 510 void dram_init_banksize(void) 511 { 512 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 513 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 514 515 switch (gd->ram_size) { 516 case 0x10000000: /* DDR_16BIT_256MB */ 517 gd->bd->bi_dram[0].size = 0x10000000; 518 gd->bd->bi_dram[1].size = 0; 519 break; 520 case 0x20000000: /* DDR_32BIT_512MB */ 521 gd->bd->bi_dram[0].size = 0x20000000; 522 gd->bd->bi_dram[1].size = 0; 523 break; 524 case 0x40000000: 525 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */ 526 gd->bd->bi_dram[0].size = 0x20000000; 527 gd->bd->bi_dram[1].size = 0x20000000; 528 } else { /* DDR_64BIT_1GB */ 529 gd->bd->bi_dram[0].size = 0x40000000; 530 gd->bd->bi_dram[1].size = 0; 531 } 532 break; 533 case 0x80000000: /* DDR_64BIT_2GB */ 534 gd->bd->bi_dram[0].size = 0x40000000; 535 gd->bd->bi_dram[1].size = 0x40000000; 536 break; 537 case 0xEFF00000: /* DDR_64BIT_4GB */ 538 gd->bd->bi_dram[0].size = 0x70000000; 539 gd->bd->bi_dram[1].size = 0x7FF00000; 540 break; 541 } 542 } 543 544 int dram_init(void) 545 { 546 gd->ram_size = imx_ddr_size(); 547 switch (gd->ram_size) { 548 case 0x10000000: 549 case 0x20000000: 550 case 0x40000000: 551 case 0x80000000: 552 break; 553 case 0xF0000000: 554 gd->ram_size -= 0x100000; 555 break; 556 default: 557 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size); 558 return -1; 559 } 560 561 return 0; 562 } 563 564 u32 get_board_rev(void) 565 { 566 return cl_eeprom_get_board_rev(); 567 } 568 569 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = { 570 .reg = (struct mxc_uart *)UART4_BASE, 571 }; 572 573 U_BOOT_DEVICE(cm_fx6_serial) = { 574 .name = "serial_mxc", 575 .platdata = &cm_fx6_mxc_serial_plat, 576 }; 577