1 /* 2 * Board functions for Compulab CM-FX6 board 3 * 4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ 5 * 6 * Author: Nikita Kiryanov <nikita@compulab.co.il> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <ahci.h> 13 #include <dm.h> 14 #include <dwc_ahsata.h> 15 #include <environment.h> 16 #include <fsl_esdhc.h> 17 #include <miiphy.h> 18 #include <mtd_node.h> 19 #include <netdev.h> 20 #include <errno.h> 21 #include <usb.h> 22 #include <fdt_support.h> 23 #include <sata.h> 24 #include <splash.h> 25 #include <asm/arch/crm_regs.h> 26 #include <asm/arch/sys_proto.h> 27 #include <asm/arch/iomux.h> 28 #include <asm/arch/mxc_hdmi.h> 29 #include <asm/mach-imx/mxc_i2c.h> 30 #include <asm/mach-imx/sata.h> 31 #include <asm/mach-imx/video.h> 32 #include <asm/io.h> 33 #include <asm/gpio.h> 34 #include <dm/platform_data/serial_mxc.h> 35 #include <dm/device-internal.h> 36 #include <jffs2/load_kernel.h> 37 #include "common.h" 38 #include "../common/eeprom.h" 39 #include "../common/common.h" 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 #ifdef CONFIG_SPLASH_SCREEN 44 static struct splash_location cm_fx6_splash_locations[] = { 45 { 46 .name = "sf", 47 .storage = SPLASH_STORAGE_SF, 48 .flags = SPLASH_STORAGE_RAW, 49 .offset = 0x100000, 50 }, 51 { 52 .name = "mmc_fs", 53 .storage = SPLASH_STORAGE_MMC, 54 .flags = SPLASH_STORAGE_FS, 55 .devpart = "2:1", 56 }, 57 { 58 .name = "usb_fs", 59 .storage = SPLASH_STORAGE_USB, 60 .flags = SPLASH_STORAGE_FS, 61 .devpart = "0:1", 62 }, 63 { 64 .name = "sata_fs", 65 .storage = SPLASH_STORAGE_SATA, 66 .flags = SPLASH_STORAGE_FS, 67 .devpart = "0:1", 68 }, 69 }; 70 71 int splash_screen_prepare(void) 72 { 73 return splash_source_load(cm_fx6_splash_locations, 74 ARRAY_SIZE(cm_fx6_splash_locations)); 75 } 76 #endif 77 78 #ifdef CONFIG_IMX_HDMI 79 static void cm_fx6_enable_hdmi(struct display_info_t const *dev) 80 { 81 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 82 imx_setup_hdmi(); 83 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK); 84 imx_enable_hdmi_phy(); 85 } 86 87 static struct display_info_t preset_hdmi_1024X768 = { 88 .bus = -1, 89 .addr = 0, 90 .pixfmt = IPU_PIX_FMT_RGB24, 91 .enable = cm_fx6_enable_hdmi, 92 .mode = { 93 .name = "HDMI", 94 .refresh = 60, 95 .xres = 1024, 96 .yres = 768, 97 .pixclock = 40385, 98 .left_margin = 220, 99 .right_margin = 40, 100 .upper_margin = 21, 101 .lower_margin = 7, 102 .hsync_len = 60, 103 .vsync_len = 10, 104 .sync = FB_SYNC_EXT, 105 .vmode = FB_VMODE_NONINTERLACED, 106 } 107 }; 108 109 static void cm_fx6_setup_display(void) 110 { 111 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 112 113 enable_ipu_clock(); 114 clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK); 115 } 116 117 int board_video_skip(void) 118 { 119 int ret; 120 struct display_info_t *preset; 121 char const *panel = env_get("displaytype"); 122 123 if (!panel) /* Also accept panel for backward compatibility */ 124 panel = env_get("panel"); 125 126 if (!panel) 127 return -ENOENT; 128 129 if (!strcmp(panel, "HDMI")) 130 preset = &preset_hdmi_1024X768; 131 else 132 return -EINVAL; 133 134 ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt); 135 if (ret) { 136 printf("Can't init display %s: %d\n", preset->mode.name, ret); 137 return ret; 138 } 139 140 preset->enable(preset); 141 printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres, 142 preset->mode.yres); 143 144 return 0; 145 } 146 #else 147 static inline void cm_fx6_setup_display(void) {} 148 #endif /* CONFIG_VIDEO_IPUV3 */ 149 150 #ifdef CONFIG_DWC_AHSATA 151 static int cm_fx6_issd_gpios[] = { 152 /* The order of the GPIOs in the array is important! */ 153 CM_FX6_SATA_LDO_EN, 154 CM_FX6_SATA_PHY_SLP, 155 CM_FX6_SATA_NRSTDLY, 156 CM_FX6_SATA_PWREN, 157 CM_FX6_SATA_NSTANDBY1, 158 CM_FX6_SATA_NSTANDBY2, 159 }; 160 161 static void cm_fx6_sata_power(int on) 162 { 163 int i; 164 165 if (!on) { /* tell the iSSD that the power will be removed */ 166 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1); 167 mdelay(10); 168 } 169 170 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { 171 gpio_direction_output(cm_fx6_issd_gpios[i], on); 172 udelay(100); 173 } 174 175 if (!on) /* for compatibility lower the power loss interrupt */ 176 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); 177 } 178 179 static iomux_v3_cfg_t const sata_pads[] = { 180 /* SATA PWR */ 181 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), 182 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), 183 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), 184 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 185 /* SATA CTRL */ 186 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), 187 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)), 188 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), 189 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 190 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), 191 }; 192 193 static int cm_fx6_setup_issd(void) 194 { 195 int ret, i; 196 197 SETUP_IOMUX_PADS(sata_pads); 198 199 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { 200 ret = gpio_request(cm_fx6_issd_gpios[i], "sata"); 201 if (ret) 202 return ret; 203 } 204 205 ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int"); 206 if (ret) 207 return ret; 208 209 return 0; 210 } 211 212 #define CM_FX6_SATA_INIT_RETRIES 10 213 214 #else 215 static int cm_fx6_setup_issd(void) { return 0; } 216 #endif 217 218 #ifdef CONFIG_SYS_I2C_MXC 219 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 220 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 221 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 222 223 I2C_PADS(i2c0_pads, 224 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), 225 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL), 226 IMX_GPIO_NR(3, 21), 227 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), 228 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL), 229 IMX_GPIO_NR(3, 28)); 230 231 I2C_PADS(i2c1_pads, 232 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), 233 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), 234 IMX_GPIO_NR(4, 12), 235 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), 236 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), 237 IMX_GPIO_NR(4, 13)); 238 239 I2C_PADS(i2c2_pads, 240 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), 241 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL), 242 IMX_GPIO_NR(1, 3), 243 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), 244 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL), 245 IMX_GPIO_NR(1, 6)); 246 247 248 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads) 249 { 250 int ret; 251 252 ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads); 253 if (ret) 254 printf("Warning: I2C%d setup failed: %d\n", busnum, ret); 255 256 return ret; 257 } 258 259 static int cm_fx6_setup_i2c(void) 260 { 261 int ret = 0, err; 262 263 /* i2c<x>_pads are wierd macro variables; we can't use an array */ 264 err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads)); 265 if (err) 266 ret = err; 267 err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads)); 268 if (err) 269 ret = err; 270 err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads)); 271 if (err) 272 ret = err; 273 274 return ret; 275 } 276 #else 277 static int cm_fx6_setup_i2c(void) { return 0; } 278 #endif 279 280 #ifdef CONFIG_USB_EHCI_MX6 281 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ 282 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 283 PAD_CTL_HYS | PAD_CTL_SRE_SLOW) 284 #define MX6_USBNC_BASEADDR 0x2184800 285 #define USBNC_USB_H1_PWR_POL (1 << 9) 286 287 static int cm_fx6_setup_usb_host(void) 288 { 289 int err; 290 291 err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst"); 292 if (err) 293 return err; 294 295 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)); 296 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)); 297 298 return 0; 299 } 300 301 static int cm_fx6_setup_usb_otg(void) 302 { 303 int err; 304 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 305 306 err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr"); 307 if (err) { 308 printf("USB OTG pwr gpio request failed: %d\n", err); 309 return err; 310 } 311 312 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL)); 313 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID | 314 MUX_PAD_CTRL(WEAK_PULLDOWN)); 315 clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK); 316 /* disable ext. charger detect, or it'll affect signal quality at dp. */ 317 return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0); 318 } 319 320 int board_usb_phy_mode(int port) 321 { 322 return USB_INIT_HOST; 323 } 324 325 int board_ehci_hcd_init(int port) 326 { 327 int ret; 328 u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4); 329 330 /* Only 1 host controller in use. port 0 is OTG & needs no attention */ 331 if (port != 1) 332 return 0; 333 334 /* Set PWR polarity to match power switch's enable polarity */ 335 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL); 336 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0); 337 if (ret) 338 return ret; 339 340 udelay(10); 341 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1); 342 if (ret) 343 return ret; 344 345 mdelay(1); 346 347 return 0; 348 } 349 350 int board_ehci_power(int port, int on) 351 { 352 if (port == 0) 353 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on); 354 355 return 0; 356 } 357 #else 358 static int cm_fx6_setup_usb_otg(void) { return 0; } 359 static int cm_fx6_setup_usb_host(void) { return 0; } 360 #endif 361 362 #ifdef CONFIG_FEC_MXC 363 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 364 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 365 366 static int mx6_rgmii_rework(struct phy_device *phydev) 367 { 368 unsigned short val; 369 370 /* Ar8031 phy SmartEEE feature cause link status generates glitch, 371 * which cause ethernet link down/up issue, so disable SmartEEE 372 */ 373 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); 374 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); 375 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); 376 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 377 val &= ~(0x1 << 8); 378 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 379 380 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 381 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 382 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 383 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 384 385 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 386 val &= 0xffe3; 387 val |= 0x18; 388 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 389 390 /* introduce tx clock delay */ 391 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 392 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 393 val |= 0x0100; 394 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 395 396 return 0; 397 } 398 399 int board_phy_config(struct phy_device *phydev) 400 { 401 mx6_rgmii_rework(phydev); 402 403 if (phydev->drv->config) 404 return phydev->drv->config(phydev); 405 406 return 0; 407 } 408 409 static iomux_v3_cfg_t const enet_pads[] = { 410 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 411 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 412 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 413 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 414 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 415 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 416 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 417 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 418 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 419 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 420 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 421 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 422 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)), 423 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)), 424 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)), 425 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | 426 MUX_PAD_CTRL(ENET_PAD_CTRL)), 427 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | 428 MUX_PAD_CTRL(ENET_PAD_CTRL)), 429 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | 430 MUX_PAD_CTRL(ENET_PAD_CTRL)), 431 }; 432 433 static int handle_mac_address(char *env_var, uint eeprom_bus) 434 { 435 unsigned char enetaddr[6]; 436 int rc; 437 438 rc = eth_env_get_enetaddr(env_var, enetaddr); 439 if (rc) 440 return 0; 441 442 rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus); 443 if (rc) 444 return rc; 445 446 if (!is_valid_ethaddr(enetaddr)) 447 return -1; 448 449 return eth_env_set_enetaddr(env_var, enetaddr); 450 } 451 452 #define SB_FX6_I2C_EEPROM_BUS 0 453 #define NO_MAC_ADDR "No MAC address found for %s\n" 454 int board_eth_init(bd_t *bis) 455 { 456 int err; 457 458 if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS)) 459 printf(NO_MAC_ADDR, "primary NIC"); 460 461 if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS)) 462 printf(NO_MAC_ADDR, "secondary NIC"); 463 464 SETUP_IOMUX_PADS(enet_pads); 465 /* phy reset */ 466 err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst"); 467 if (err) 468 printf("Etnernet NRST gpio request failed: %d\n", err); 469 gpio_direction_output(CM_FX6_ENET_NRST, 0); 470 udelay(500); 471 gpio_set_value(CM_FX6_ENET_NRST, 1); 472 enable_enet_clk(1); 473 return cpu_eth_init(bis); 474 } 475 #endif 476 477 #ifdef CONFIG_NAND_MXS 478 static iomux_v3_cfg_t const nand_pads[] = { 479 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), 480 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), 481 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 482 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 483 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), 484 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), 485 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 486 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), 487 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), 488 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), 489 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 490 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), 491 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 492 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 493 }; 494 495 static void cm_fx6_setup_gpmi_nand(void) 496 { 497 SETUP_IOMUX_PADS(nand_pads); 498 /* Enable clock roots */ 499 enable_usdhc_clk(1, 3); 500 enable_usdhc_clk(1, 4); 501 502 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) | 503 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) | 504 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0)); 505 } 506 #else 507 static void cm_fx6_setup_gpmi_nand(void) {} 508 #endif 509 510 #ifdef CONFIG_MXC_SPI 511 int cm_fx6_setup_ecspi(void) 512 { 513 cm_fx6_set_ecspi_iomux(); 514 return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0"); 515 } 516 #else 517 int cm_fx6_setup_ecspi(void) { return 0; } 518 #endif 519 520 #ifdef CONFIG_OF_BOARD_SETUP 521 #define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/" 522 523 struct node_info nodes[] = { 524 /* 525 * Both entries target the same flash chip. The st,m25p compatible 526 * is used in the vendor device trees, while upstream uses (the 527 * documented) jedec,spi-nor compatible. 528 */ 529 { "st,m25p", MTD_DEV_TYPE_NOR, }, 530 { "jedec,spi-nor", MTD_DEV_TYPE_NOR, }, 531 }; 532 533 int ft_board_setup(void *blob, bd_t *bd) 534 { 535 u32 baseboard_rev; 536 int nodeoffset; 537 uint8_t enetaddr[6]; 538 char baseboard_name[16]; 539 int err; 540 541 fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */ 542 543 /* MAC addr */ 544 if (eth_env_get_enetaddr("ethaddr", enetaddr)) { 545 fdt_find_and_setprop(blob, 546 "/soc/aips-bus@02100000/ethernet@02188000", 547 "local-mac-address", enetaddr, 6, 1); 548 } 549 550 if (eth_env_get_enetaddr("eth1addr", enetaddr)) { 551 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address", 552 enetaddr, 6, 1); 553 } 554 555 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 556 557 baseboard_rev = cl_eeprom_get_board_rev(0); 558 err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0); 559 if (err || baseboard_rev == 0) 560 return 0; /* Assume not an early revision SB-FX6m baseboard */ 561 562 if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) { 563 nodeoffset = fdt_path_offset(blob, USDHC3_PATH); 564 fdt_delprop(blob, nodeoffset, "cd-gpios"); 565 fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd", 566 NULL, 0, 1); 567 fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend", 568 NULL, 0, 1); 569 } 570 571 return 0; 572 } 573 #endif 574 575 int board_init(void) 576 { 577 int ret; 578 579 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 580 cm_fx6_setup_gpmi_nand(); 581 582 ret = cm_fx6_setup_ecspi(); 583 if (ret) 584 printf("Warning: ECSPI setup failed: %d\n", ret); 585 586 ret = cm_fx6_setup_usb_otg(); 587 if (ret) 588 printf("Warning: USB OTG setup failed: %d\n", ret); 589 590 ret = cm_fx6_setup_usb_host(); 591 if (ret) 592 printf("Warning: USB host setup failed: %d\n", ret); 593 594 /* 595 * cm-fx6 may have iSSD not assembled and in this case it has 596 * bypasses for a (m)SATA socket on the baseboard. The socketed 597 * device is not controlled by those GPIOs. So just print a warning 598 * if the setup fails. 599 */ 600 ret = cm_fx6_setup_issd(); 601 if (ret) 602 printf("Warning: iSSD setup failed: %d\n", ret); 603 604 /* Warn on failure but do not abort boot */ 605 ret = cm_fx6_setup_i2c(); 606 if (ret) 607 printf("Warning: I2C setup failed: %d\n", ret); 608 609 cm_fx6_setup_display(); 610 611 /* This should be done in the MMC driver when MX6 has a clock driver */ 612 #ifdef CONFIG_FSL_ESDHC 613 if (IS_ENABLED(CONFIG_BLK)) { 614 int i; 615 616 cm_fx6_set_usdhc_iomux(); 617 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) 618 enable_usdhc_clk(1, i); 619 } 620 #endif 621 622 return 0; 623 } 624 625 int board_late_init(void) 626 { 627 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 628 char baseboard_name[16]; 629 int err; 630 631 if (is_mx6dq()) 632 env_set("board_rev", "MX6Q"); 633 else if (is_mx6dl()) 634 env_set("board_rev", "MX6DL"); 635 636 err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0); 637 if (err) 638 return 0; 639 640 if (!strncmp("SB-FX6m", baseboard_name, 7)) 641 env_set("board_name", "Utilite"); 642 #endif 643 return 0; 644 } 645 646 int checkboard(void) 647 { 648 puts("Board: CM-FX6\n"); 649 return 0; 650 } 651 652 int misc_init_r(void) 653 { 654 cl_print_pcb_info(); 655 656 return 0; 657 } 658 659 int dram_init_banksize(void) 660 { 661 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 662 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 663 664 switch (gd->ram_size) { 665 case 0x10000000: /* DDR_16BIT_256MB */ 666 gd->bd->bi_dram[0].size = 0x10000000; 667 gd->bd->bi_dram[1].size = 0; 668 break; 669 case 0x20000000: /* DDR_32BIT_512MB */ 670 gd->bd->bi_dram[0].size = 0x20000000; 671 gd->bd->bi_dram[1].size = 0; 672 break; 673 case 0x40000000: 674 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */ 675 gd->bd->bi_dram[0].size = 0x20000000; 676 gd->bd->bi_dram[1].size = 0x20000000; 677 } else { /* DDR_64BIT_1GB */ 678 gd->bd->bi_dram[0].size = 0x40000000; 679 gd->bd->bi_dram[1].size = 0; 680 } 681 break; 682 case 0x80000000: /* DDR_64BIT_2GB */ 683 gd->bd->bi_dram[0].size = 0x40000000; 684 gd->bd->bi_dram[1].size = 0x40000000; 685 break; 686 case 0xEFF00000: /* DDR_64BIT_4GB */ 687 gd->bd->bi_dram[0].size = 0x70000000; 688 gd->bd->bi_dram[1].size = 0x7FF00000; 689 break; 690 } 691 692 return 0; 693 } 694 695 int dram_init(void) 696 { 697 gd->ram_size = imx_ddr_size(); 698 switch (gd->ram_size) { 699 case 0x10000000: 700 case 0x20000000: 701 case 0x40000000: 702 case 0x80000000: 703 break; 704 case 0xF0000000: 705 gd->ram_size -= 0x100000; 706 break; 707 default: 708 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size); 709 return -1; 710 } 711 712 return 0; 713 } 714 715 u32 get_board_rev(void) 716 { 717 return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS); 718 } 719 720 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = { 721 .reg = (struct mxc_uart *)UART4_BASE, 722 }; 723 724 U_BOOT_DEVICE(cm_fx6_serial) = { 725 .name = "serial_mxc", 726 .platdata = &cm_fx6_mxc_serial_plat, 727 }; 728 729 #if CONFIG_IS_ENABLED(AHCI) 730 static int sata_imx_probe(struct udevice *dev) 731 { 732 int i, err; 733 734 /* Make sure this gpio has logical 0 value */ 735 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); 736 udelay(100); 737 cm_fx6_sata_power(1); 738 739 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) { 740 err = setup_sata(); 741 if (err) { 742 printf("SATA setup failed: %d\n", err); 743 return err; 744 } 745 746 udelay(100); 747 748 err = dwc_ahsata_probe(dev); 749 if (!err) 750 break; 751 752 /* There is no device on the SATA port */ 753 if (sata_dm_port_status(0, 0) == 0) 754 break; 755 756 /* There's a device, but link not established. Retry */ 757 device_remove(dev, DM_REMOVE_NORMAL); 758 } 759 760 return 0; 761 } 762 763 static int sata_imx_remove(struct udevice *dev) 764 { 765 cm_fx6_sata_power(0); 766 mdelay(250); 767 768 return 0; 769 } 770 771 struct ahci_ops sata_imx_ops = { 772 .port_status = dwc_ahsata_port_status, 773 .reset = dwc_ahsata_bus_reset, 774 .scan = dwc_ahsata_scan, 775 }; 776 777 static const struct udevice_id sata_imx_ids[] = { 778 { .compatible = "fsl,imx6q-ahci" }, 779 { } 780 }; 781 782 U_BOOT_DRIVER(sata_imx) = { 783 .name = "dwc_ahci", 784 .id = UCLASS_AHCI, 785 .of_match = sata_imx_ids, 786 .ops = &sata_imx_ops, 787 .probe = sata_imx_probe, 788 .remove = sata_imx_remove, /* reset bus to stop it */ 789 }; 790 #endif /* AHCI */ 791