1 /* 2 * Board functions for Compulab CM-FX6 board 3 * 4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ 5 * 6 * Author: Nikita Kiryanov <nikita@compulab.co.il> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <fsl_esdhc.h> 14 #include <miiphy.h> 15 #include <netdev.h> 16 #include <errno.h> 17 #include <fdt_support.h> 18 #include <sata.h> 19 #include <splash.h> 20 #include <asm/arch/crm_regs.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/iomux.h> 23 #include <asm/arch/mxc_hdmi.h> 24 #include <asm/imx-common/mxc_i2c.h> 25 #include <asm/imx-common/sata.h> 26 #include <asm/imx-common/video.h> 27 #include <asm/io.h> 28 #include <asm/gpio.h> 29 #include <dm/platform_data/serial_mxc.h> 30 #include "common.h" 31 #include "../common/eeprom.h" 32 #include "../common/common.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #ifdef CONFIG_SPLASH_SCREEN 37 static struct splash_location cm_fx6_splash_locations[] = { 38 { 39 .name = "sf", 40 .storage = SPLASH_STORAGE_SF, 41 .offset = 0x100000, 42 }, 43 }; 44 45 int splash_screen_prepare(void) 46 { 47 return splash_source_load(cm_fx6_splash_locations, 48 ARRAY_SIZE(cm_fx6_splash_locations)); 49 } 50 #endif 51 52 #ifdef CONFIG_IMX_HDMI 53 static void cm_fx6_enable_hdmi(struct display_info_t const *dev) 54 { 55 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 56 imx_setup_hdmi(); 57 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK); 58 imx_enable_hdmi_phy(); 59 } 60 61 static struct display_info_t preset_hdmi_1024X768 = { 62 .bus = -1, 63 .addr = 0, 64 .pixfmt = IPU_PIX_FMT_RGB24, 65 .enable = cm_fx6_enable_hdmi, 66 .mode = { 67 .name = "HDMI", 68 .refresh = 60, 69 .xres = 1024, 70 .yres = 768, 71 .pixclock = 40385, 72 .left_margin = 220, 73 .right_margin = 40, 74 .upper_margin = 21, 75 .lower_margin = 7, 76 .hsync_len = 60, 77 .vsync_len = 10, 78 .sync = FB_SYNC_EXT, 79 .vmode = FB_VMODE_NONINTERLACED, 80 } 81 }; 82 83 static void cm_fx6_setup_display(void) 84 { 85 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 86 87 enable_ipu_clock(); 88 clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK); 89 } 90 91 int board_video_skip(void) 92 { 93 int ret; 94 struct display_info_t *preset; 95 char const *panel = getenv("displaytype"); 96 97 if (!panel) /* Also accept panel for backward compatibility */ 98 panel = getenv("panel"); 99 100 if (!panel) 101 return -ENOENT; 102 103 if (!strcmp(panel, "HDMI")) 104 preset = &preset_hdmi_1024X768; 105 else 106 return -EINVAL; 107 108 ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt); 109 if (ret) { 110 printf("Can't init display %s: %d\n", preset->mode.name, ret); 111 return ret; 112 } 113 114 preset->enable(preset); 115 printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres, 116 preset->mode.yres); 117 118 return 0; 119 } 120 #else 121 static inline void cm_fx6_setup_display(void) {} 122 #endif /* CONFIG_VIDEO_IPUV3 */ 123 124 #ifdef CONFIG_DWC_AHSATA 125 static int cm_fx6_issd_gpios[] = { 126 /* The order of the GPIOs in the array is important! */ 127 CM_FX6_SATA_LDO_EN, 128 CM_FX6_SATA_PHY_SLP, 129 CM_FX6_SATA_NRSTDLY, 130 CM_FX6_SATA_PWREN, 131 CM_FX6_SATA_NSTANDBY1, 132 CM_FX6_SATA_NSTANDBY2, 133 }; 134 135 static void cm_fx6_sata_power(int on) 136 { 137 int i; 138 139 if (!on) { /* tell the iSSD that the power will be removed */ 140 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1); 141 mdelay(10); 142 } 143 144 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { 145 gpio_direction_output(cm_fx6_issd_gpios[i], on); 146 udelay(100); 147 } 148 149 if (!on) /* for compatibility lower the power loss interrupt */ 150 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); 151 } 152 153 static iomux_v3_cfg_t const sata_pads[] = { 154 /* SATA PWR */ 155 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), 156 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), 157 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), 158 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 159 /* SATA CTRL */ 160 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), 161 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)), 162 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), 163 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 164 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), 165 }; 166 167 static int cm_fx6_setup_issd(void) 168 { 169 int ret, i; 170 171 SETUP_IOMUX_PADS(sata_pads); 172 173 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) { 174 ret = gpio_request(cm_fx6_issd_gpios[i], "sata"); 175 if (ret) 176 return ret; 177 } 178 179 ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int"); 180 if (ret) 181 return ret; 182 183 return 0; 184 } 185 186 #define CM_FX6_SATA_INIT_RETRIES 10 187 int sata_initialize(void) 188 { 189 int err, i; 190 191 /* Make sure this gpio has logical 0 value */ 192 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0); 193 udelay(100); 194 cm_fx6_sata_power(1); 195 196 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) { 197 err = setup_sata(); 198 if (err) { 199 printf("SATA setup failed: %d\n", err); 200 return err; 201 } 202 203 udelay(100); 204 205 err = __sata_initialize(); 206 if (!err) 207 break; 208 209 /* There is no device on the SATA port */ 210 if (sata_port_status(0, 0) == 0) 211 break; 212 213 /* There's a device, but link not established. Retry */ 214 } 215 216 return err; 217 } 218 219 int sata_stop(void) 220 { 221 __sata_stop(); 222 cm_fx6_sata_power(0); 223 mdelay(250); 224 225 return 0; 226 } 227 #else 228 static int cm_fx6_setup_issd(void) { return 0; } 229 #endif 230 231 #ifdef CONFIG_SYS_I2C_MXC 232 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 233 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 234 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 235 236 I2C_PADS(i2c0_pads, 237 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), 238 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL), 239 IMX_GPIO_NR(3, 21), 240 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), 241 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL), 242 IMX_GPIO_NR(3, 28)); 243 244 I2C_PADS(i2c1_pads, 245 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), 246 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL), 247 IMX_GPIO_NR(4, 12), 248 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), 249 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL), 250 IMX_GPIO_NR(4, 13)); 251 252 I2C_PADS(i2c2_pads, 253 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), 254 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL), 255 IMX_GPIO_NR(1, 3), 256 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), 257 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL), 258 IMX_GPIO_NR(1, 6)); 259 260 261 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads) 262 { 263 int ret; 264 265 ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads); 266 if (ret) 267 printf("Warning: I2C%d setup failed: %d\n", busnum, ret); 268 269 return ret; 270 } 271 272 static int cm_fx6_setup_i2c(void) 273 { 274 int ret = 0, err; 275 276 /* i2c<x>_pads are wierd macro variables; we can't use an array */ 277 err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads)); 278 if (err) 279 ret = err; 280 err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads)); 281 if (err) 282 ret = err; 283 err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads)); 284 if (err) 285 ret = err; 286 287 return ret; 288 } 289 #else 290 static int cm_fx6_setup_i2c(void) { return 0; } 291 #endif 292 293 #ifdef CONFIG_USB_EHCI_MX6 294 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ 295 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 296 PAD_CTL_HYS | PAD_CTL_SRE_SLOW) 297 #define MX6_USBNC_BASEADDR 0x2184800 298 #define USBNC_USB_H1_PWR_POL (1 << 9) 299 300 static int cm_fx6_setup_usb_host(void) 301 { 302 int err; 303 304 err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst"); 305 if (err) 306 return err; 307 308 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)); 309 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)); 310 311 return 0; 312 } 313 314 static int cm_fx6_setup_usb_otg(void) 315 { 316 int err; 317 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 318 319 err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr"); 320 if (err) { 321 printf("USB OTG pwr gpio request failed: %d\n", err); 322 return err; 323 } 324 325 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL)); 326 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID | 327 MUX_PAD_CTRL(WEAK_PULLDOWN)); 328 clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK); 329 /* disable ext. charger detect, or it'll affect signal quality at dp. */ 330 return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0); 331 } 332 333 int board_ehci_hcd_init(int port) 334 { 335 int ret; 336 u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4); 337 338 /* Only 1 host controller in use. port 0 is OTG & needs no attention */ 339 if (port != 1) 340 return 0; 341 342 /* Set PWR polarity to match power switch's enable polarity */ 343 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL); 344 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0); 345 if (ret) 346 return ret; 347 348 udelay(10); 349 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1); 350 if (ret) 351 return ret; 352 353 mdelay(1); 354 355 return 0; 356 } 357 358 int board_ehci_power(int port, int on) 359 { 360 if (port == 0) 361 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on); 362 363 return 0; 364 } 365 #else 366 static int cm_fx6_setup_usb_otg(void) { return 0; } 367 static int cm_fx6_setup_usb_host(void) { return 0; } 368 #endif 369 370 #ifdef CONFIG_FEC_MXC 371 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 372 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 373 374 static int mx6_rgmii_rework(struct phy_device *phydev) 375 { 376 unsigned short val; 377 378 /* Ar8031 phy SmartEEE feature cause link status generates glitch, 379 * which cause ethernet link down/up issue, so disable SmartEEE 380 */ 381 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); 382 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); 383 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); 384 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 385 val &= ~(0x1 << 8); 386 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 387 388 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 389 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 390 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 391 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 392 393 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 394 val &= 0xffe3; 395 val |= 0x18; 396 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 397 398 /* introduce tx clock delay */ 399 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 400 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 401 val |= 0x0100; 402 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 403 404 return 0; 405 } 406 407 int board_phy_config(struct phy_device *phydev) 408 { 409 mx6_rgmii_rework(phydev); 410 411 if (phydev->drv->config) 412 return phydev->drv->config(phydev); 413 414 return 0; 415 } 416 417 static iomux_v3_cfg_t const enet_pads[] = { 418 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 419 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 420 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 421 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 422 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 423 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 424 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 425 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 426 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 427 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 428 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 429 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 430 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)), 431 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)), 432 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)), 433 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | 434 MUX_PAD_CTRL(ENET_PAD_CTRL)), 435 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | 436 MUX_PAD_CTRL(ENET_PAD_CTRL)), 437 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | 438 MUX_PAD_CTRL(ENET_PAD_CTRL)), 439 }; 440 441 static int handle_mac_address(char *env_var, uint eeprom_bus) 442 { 443 unsigned char enetaddr[6]; 444 int rc; 445 446 rc = eth_getenv_enetaddr(env_var, enetaddr); 447 if (rc) 448 return 0; 449 450 rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus); 451 if (rc) 452 return rc; 453 454 if (!is_valid_ethaddr(enetaddr)) 455 return -1; 456 457 return eth_setenv_enetaddr(env_var, enetaddr); 458 } 459 460 #define SB_FX6_I2C_EEPROM_BUS 0 461 #define NO_MAC_ADDR "No MAC address found for %s\n" 462 int board_eth_init(bd_t *bis) 463 { 464 int err; 465 466 if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS)) 467 printf(NO_MAC_ADDR, "primary NIC"); 468 469 if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS)) 470 printf(NO_MAC_ADDR, "secondary NIC"); 471 472 SETUP_IOMUX_PADS(enet_pads); 473 /* phy reset */ 474 err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst"); 475 if (err) 476 printf("Etnernet NRST gpio request failed: %d\n", err); 477 gpio_direction_output(CM_FX6_ENET_NRST, 0); 478 udelay(500); 479 gpio_set_value(CM_FX6_ENET_NRST, 1); 480 enable_enet_clk(1); 481 return cpu_eth_init(bis); 482 } 483 #endif 484 485 #ifdef CONFIG_NAND_MXS 486 static iomux_v3_cfg_t const nand_pads[] = { 487 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), 488 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), 489 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 490 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 491 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), 492 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), 493 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 494 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), 495 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), 496 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), 497 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), 498 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), 499 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 500 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), 501 }; 502 503 static void cm_fx6_setup_gpmi_nand(void) 504 { 505 SETUP_IOMUX_PADS(nand_pads); 506 /* Enable clock roots */ 507 enable_usdhc_clk(1, 3); 508 enable_usdhc_clk(1, 4); 509 510 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) | 511 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) | 512 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0)); 513 } 514 #else 515 static void cm_fx6_setup_gpmi_nand(void) {} 516 #endif 517 518 #ifdef CONFIG_FSL_ESDHC 519 static struct fsl_esdhc_cfg usdhc_cfg[3] = { 520 {USDHC1_BASE_ADDR}, 521 {USDHC2_BASE_ADDR}, 522 {USDHC3_BASE_ADDR}, 523 }; 524 525 static enum mxc_clock usdhc_clk[3] = { 526 MXC_ESDHC_CLK, 527 MXC_ESDHC2_CLK, 528 MXC_ESDHC3_CLK, 529 }; 530 531 int board_mmc_init(bd_t *bis) 532 { 533 int i; 534 535 cm_fx6_set_usdhc_iomux(); 536 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 537 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]); 538 usdhc_cfg[i].max_bus_width = 4; 539 fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 540 enable_usdhc_clk(1, i); 541 } 542 543 return 0; 544 } 545 #endif 546 547 #ifdef CONFIG_MXC_SPI 548 int cm_fx6_setup_ecspi(void) 549 { 550 cm_fx6_set_ecspi_iomux(); 551 return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0"); 552 } 553 #else 554 int cm_fx6_setup_ecspi(void) { return 0; } 555 #endif 556 557 #ifdef CONFIG_OF_BOARD_SETUP 558 int ft_board_setup(void *blob, bd_t *bd) 559 { 560 uint8_t enetaddr[6]; 561 562 /* MAC addr */ 563 if (eth_getenv_enetaddr("ethaddr", enetaddr)) { 564 fdt_find_and_setprop(blob, 565 "/soc/aips-bus@02100000/ethernet@02188000", 566 "local-mac-address", enetaddr, 6, 1); 567 } 568 569 if (eth_getenv_enetaddr("eth1addr", enetaddr)) { 570 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address", 571 enetaddr, 6, 1); 572 } 573 574 return 0; 575 } 576 #endif 577 578 int board_init(void) 579 { 580 int ret; 581 582 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 583 cm_fx6_setup_gpmi_nand(); 584 585 ret = cm_fx6_setup_ecspi(); 586 if (ret) 587 printf("Warning: ECSPI setup failed: %d\n", ret); 588 589 ret = cm_fx6_setup_usb_otg(); 590 if (ret) 591 printf("Warning: USB OTG setup failed: %d\n", ret); 592 593 ret = cm_fx6_setup_usb_host(); 594 if (ret) 595 printf("Warning: USB host setup failed: %d\n", ret); 596 597 /* 598 * cm-fx6 may have iSSD not assembled and in this case it has 599 * bypasses for a (m)SATA socket on the baseboard. The socketed 600 * device is not controlled by those GPIOs. So just print a warning 601 * if the setup fails. 602 */ 603 ret = cm_fx6_setup_issd(); 604 if (ret) 605 printf("Warning: iSSD setup failed: %d\n", ret); 606 607 /* Warn on failure but do not abort boot */ 608 ret = cm_fx6_setup_i2c(); 609 if (ret) 610 printf("Warning: I2C setup failed: %d\n", ret); 611 612 cm_fx6_setup_display(); 613 614 return 0; 615 } 616 617 int checkboard(void) 618 { 619 puts("Board: CM-FX6\n"); 620 return 0; 621 } 622 623 void dram_init_banksize(void) 624 { 625 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 626 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 627 628 switch (gd->ram_size) { 629 case 0x10000000: /* DDR_16BIT_256MB */ 630 gd->bd->bi_dram[0].size = 0x10000000; 631 gd->bd->bi_dram[1].size = 0; 632 break; 633 case 0x20000000: /* DDR_32BIT_512MB */ 634 gd->bd->bi_dram[0].size = 0x20000000; 635 gd->bd->bi_dram[1].size = 0; 636 break; 637 case 0x40000000: 638 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */ 639 gd->bd->bi_dram[0].size = 0x20000000; 640 gd->bd->bi_dram[1].size = 0x20000000; 641 } else { /* DDR_64BIT_1GB */ 642 gd->bd->bi_dram[0].size = 0x40000000; 643 gd->bd->bi_dram[1].size = 0; 644 } 645 break; 646 case 0x80000000: /* DDR_64BIT_2GB */ 647 gd->bd->bi_dram[0].size = 0x40000000; 648 gd->bd->bi_dram[1].size = 0x40000000; 649 break; 650 case 0xEFF00000: /* DDR_64BIT_4GB */ 651 gd->bd->bi_dram[0].size = 0x70000000; 652 gd->bd->bi_dram[1].size = 0x7FF00000; 653 break; 654 } 655 } 656 657 int dram_init(void) 658 { 659 gd->ram_size = imx_ddr_size(); 660 switch (gd->ram_size) { 661 case 0x10000000: 662 case 0x20000000: 663 case 0x40000000: 664 case 0x80000000: 665 break; 666 case 0xF0000000: 667 gd->ram_size -= 0x100000; 668 break; 669 default: 670 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size); 671 return -1; 672 } 673 674 return 0; 675 } 676 677 u32 get_board_rev(void) 678 { 679 return cl_eeprom_get_board_rev(); 680 } 681 682 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = { 683 .reg = (struct mxc_uart *)UART4_BASE, 684 }; 685 686 U_BOOT_DEVICE(cm_fx6_serial) = { 687 .name = "serial_mxc", 688 .platdata = &cm_fx6_mxc_serial_plat, 689 }; 690