1 /* 2 * SPL/U-Boot mux functions for CompuLab CL-SOM-iMX7 module 3 * 4 * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com 5 * 6 * Author: Uri Mashiach <uri.mashiach@compulab.co.il> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/mach-imx/iomux-v3.h> 13 #include <asm/arch-mx7/mx7-pins.h> 14 15 #define PADS_SET(pads_array) \ 16 void cl_som_imx7_##pads_array##_set(void) \ 17 { \ 18 imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array)); \ 19 } 20 21 #ifdef CONFIG_FSL_ESDHC 22 23 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 24 PAD_CTL_HYS | PAD_CTL_PUE | \ 25 PAD_CTL_PUS_PU47KOHM) 26 27 static iomux_v3_cfg_t const usdhc1_pads[] = { 28 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 29 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 30 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 31 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 32 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 33 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 34 35 MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 36 }; 37 38 PADS_SET(usdhc1_pads) 39 40 #endif /* CONFIG_FSL_ESDHC */ 41 42 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 43 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 44 45 static iomux_v3_cfg_t const uart1_pads[] = { 46 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 47 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 48 }; 49 50 PADS_SET(uart1_pads) 51 52 #ifdef CONFIG_SPI 53 54 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SRE_SLOW | \ 55 PAD_CTL_DSE_3P3V_32OHM) 56 57 #define GPIO_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \ 58 PAD_CTL_SRE_SLOW) 59 60 static iomux_v3_cfg_t const espi1_pads[] = { 61 MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 62 MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 63 MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 64 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL), 65 }; 66 67 PADS_SET(espi1_pads) 68 69 #endif /* CONFIG_SPI */ 70 71 #ifndef CONFIG_SPL_BUILD 72 73 #ifdef CONFIG_FSL_ESDHC 74 75 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { 76 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 82 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 83 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 84 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 85 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 86 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 88 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 }; 90 91 PADS_SET(usdhc3_emmc_pads) 92 93 #endif /* CONFIG_FSL_ESDHC */ 94 95 #ifdef CONFIG_FEC_MXC 96 97 #define ENET_PAD_CTRL (PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM) 98 #define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU5KOHM) 99 100 static iomux_v3_cfg_t const phy1_rst_pads[] = { 101 /* PHY1 RST */ 102 MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(GPIO_PAD_CTRL), 103 }; 104 105 PADS_SET(phy1_rst_pads) 106 107 static iomux_v3_cfg_t const fec1_pads[] = { 108 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | 109 MUX_PAD_CTRL(ENET_PAD_CTRL), 110 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 111 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 112 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 113 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 114 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 115 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | 116 MUX_PAD_CTRL(ENET_PAD_CTRL), 117 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 118 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 119 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 120 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 121 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 122 MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 123 MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 124 }; 125 126 PADS_SET(fec1_pads) 127 128 #endif /* CONFIG_FEC_MXC */ 129 130 static iomux_v3_cfg_t const usb_otg1_pads[] = { 131 MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 132 }; 133 134 PADS_SET(usb_otg1_pads) 135 136 static iomux_v3_cfg_t const wdog_pads[] = { 137 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), 138 }; 139 140 PADS_SET(wdog_pads) 141 142 #endif /* !CONFIG_SPL_BUILD */ 143