1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SPL data and initialization for CompuLab CL-SOM-AM57x board 4 * 5 * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/ 6 * 7 * Author: Uri Mashiach <uri.mashiach@compulab.co.il> 8 */ 9 10 #include <asm/emif.h> 11 #include <asm/omap_common.h> 12 #include <asm/arch/sys_proto.h> 13 14 static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = { 15 .dmm_lisa_map_3 = 0x80740300, 16 .is_ma_present = 0x1 17 }; 18 19 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) 20 { 21 /* Disable SDRAM controller EMIF2 for single core SOC */ 22 *dmm_lisa_regs = &cl_som_am57x_lisa_regs; 23 if (omap_revision() == DRA722_ES1_0) { 24 ((struct dmm_lisa_map_regs *) *dmm_lisa_regs)->dmm_lisa_map_3 = 25 0x80640100; 26 } 27 } 28 29 static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = { 30 .sdram_config_init = 0x61852332, 31 .sdram_config = 0x61852332, 32 .sdram_config2 = 0x00000000, 33 .ref_ctrl = 0x000040f1, 34 .ref_ctrl_final = 0x00001040, 35 .sdram_tim1 = 0xeeef36f3, 36 .sdram_tim2 = 0x348f7fda, 37 .sdram_tim3 = 0x027f88a8, 38 .read_idle_ctrl = 0x00050000, 39 .zq_config = 0x1007190b, 40 .temp_alert_config = 0x00000000, 41 .emif_ddr_phy_ctlr_1_init = 0x0034400b, 42 .emif_ddr_phy_ctlr_1 = 0x0e34400b, 43 .emif_ddr_ext_phy_ctrl_1 = 0x04040100, 44 .emif_ddr_ext_phy_ctrl_2 = 0x00740074, 45 .emif_ddr_ext_phy_ctrl_3 = 0x00780078, 46 .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, 47 .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, 48 .emif_rd_wr_lvl_rmp_win = 0x00000000, 49 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 50 .emif_rd_wr_lvl_ctl = 0x00000000, 51 .emif_rd_wr_exec_thresh = 0x00000305 52 }; 53 54 /* Ext phy ctrl regs 1-35 */ 55 static const u32 cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs[] = { 56 0x10040100, 57 0x00740074, 58 0x00780078, 59 0x007c007c, 60 0x007b007b, 61 0x00800080, 62 0x00360036, 63 0x00340034, 64 0x00360036, 65 0x00350035, 66 0x00350035, 67 68 0x01ff01ff, 69 0x01ff01ff, 70 0x01ff01ff, 71 0x01ff01ff, 72 0x01ff01ff, 73 74 0x00430043, 75 0x003e003e, 76 0x004a004a, 77 0x00470047, 78 0x00400040, 79 80 0x00000000, 81 0x00600020, 82 0x40011080, 83 0x08102040, 84 85 0x00400040, 86 0x00400040, 87 0x00400040, 88 0x00400040, 89 0x00400040, 90 0x0, 91 0x0, 92 0x0, 93 0x0, 94 0x0 95 }; 96 97 static const struct emif_regs cl_som_am57x_emif2_ddr3_532mhz_emif_regs = { 98 .sdram_config_init = 0x61852332, 99 .sdram_config = 0x61852332, 100 .sdram_config2 = 0x00000000, 101 .ref_ctrl = 0x000040f1, 102 .ref_ctrl_final = 0x00001040, 103 .sdram_tim1 = 0xeeef36f3, 104 .sdram_tim2 = 0x348f7fda, 105 .sdram_tim3 = 0x027f88a8, 106 .read_idle_ctrl = 0x00050000, 107 .zq_config = 0x1007190b, 108 .temp_alert_config = 0x00000000, 109 .emif_ddr_phy_ctlr_1_init = 0x0034400b, 110 .emif_ddr_phy_ctlr_1 = 0x0e34400b, 111 .emif_ddr_ext_phy_ctrl_1 = 0x04040100, 112 .emif_ddr_ext_phy_ctrl_2 = 0x00740074, 113 .emif_ddr_ext_phy_ctrl_3 = 0x00780078, 114 .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, 115 .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, 116 .emif_rd_wr_lvl_rmp_win = 0x00000000, 117 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 118 .emif_rd_wr_lvl_ctl = 0x00000000, 119 .emif_rd_wr_exec_thresh = 0x00000305 120 }; 121 122 static const u32 cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs[] = { 123 0x10040100, 124 0x00820082, 125 0x008b008b, 126 0x00800080, 127 0x007e007e, 128 0x00800080, 129 0x00370037, 130 0x00390039, 131 0x00360036, 132 0x00370037, 133 0x00350035, 134 0x01ff01ff, 135 0x01ff01ff, 136 0x01ff01ff, 137 0x01ff01ff, 138 0x01ff01ff, 139 0x00540054, 140 0x00540054, 141 0x004e004e, 142 0x004c004c, 143 0x00400040, 144 145 0x00000000, 146 0x00600020, 147 0x40011080, 148 0x08102040, 149 150 0x00400040, 151 0x00400040, 152 0x00400040, 153 0x00400040, 154 0x00400040, 155 0x0, 156 0x0, 157 0x0, 158 0x0, 159 0x0 160 }; 161 162 static struct vcores_data cl_som_am57x_volts = { 163 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 164 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 165 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 166 .mpu.addr = TPS659038_REG_ADDR_SMPS12, 167 .mpu.pmic = &tps659038, 168 169 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 170 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 171 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 172 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 173 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 174 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 175 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 176 .eve.addr = TPS659038_REG_ADDR_SMPS45, 177 .eve.pmic = &tps659038, 178 179 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 180 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 181 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 182 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 183 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 184 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 185 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 186 .gpu.addr = TPS659038_REG_ADDR_SMPS6, 187 .gpu.pmic = &tps659038, 188 189 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 190 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 191 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 192 .core.addr = TPS659038_REG_ADDR_SMPS7, 193 .core.pmic = &tps659038, 194 195 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 196 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 197 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 198 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 199 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 200 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 201 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 202 .iva.addr = TPS659038_REG_ADDR_SMPS8, 203 .iva.pmic = &tps659038, 204 }; 205 206 void hw_data_init(void) 207 { 208 *prcm = &dra7xx_prcm; 209 *dplls_data = &dra7xx_dplls; 210 *omap_vcores = &cl_som_am57x_volts; 211 *ctrl = &dra7xx_ctrl; 212 } 213 214 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 215 { 216 switch (emif_nr) { 217 case 1: 218 *regs = &cl_som_am57x_emif1_ddr3_532mhz_emif_regs; 219 break; 220 case 2: 221 *regs = &cl_som_am57x_emif2_ddr3_532mhz_emif_regs; 222 break; 223 } 224 } 225 226 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) 227 { 228 switch (emif_nr) { 229 case 1: 230 *regs = cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs; 231 *size = ARRAY_SIZE(cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs); 232 break; 233 case 2: 234 *regs = cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs; 235 *size = ARRAY_SIZE(cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs); 236 break; 237 } 238 } 239