1 /* 2 * Ethernet specific code for CompuLab CL-SOM-AM57x module 3 * 4 * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/ 5 * 6 * Author: Uri Mashiach <uri.mashiach@compulab.co.il> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <cpsw.h> 13 #include <environment.h> 14 #include <miiphy.h> 15 #include <asm/gpio.h> 16 #include <asm/arch/sys_proto.h> 17 #include "../common/eeprom.h" 18 19 static void cpsw_control(int enabled) 20 { 21 /* VTP can be added here */ 22 } 23 24 static struct cpsw_slave_data cl_som_am57x_cpsw_slaves[] = { 25 { 26 .slave_reg_ofs = 0x208, 27 .sliver_reg_ofs = 0xd80, 28 .phy_addr = 0, 29 .phy_if = PHY_INTERFACE_MODE_RMII, 30 }, 31 { 32 .slave_reg_ofs = 0x308, 33 .sliver_reg_ofs = 0xdc0, 34 .phy_addr = 1, 35 .phy_if = PHY_INTERFACE_MODE_RMII, 36 37 }, 38 }; 39 40 static struct cpsw_platform_data cl_som_am57_cpsw_data = { 41 .mdio_base = CPSW_MDIO_BASE, 42 .cpsw_base = CPSW_BASE, 43 .mdio_div = 0xff, 44 .channels = 8, 45 .cpdma_reg_ofs = 0x800, 46 .slaves = 2, 47 .slave_data = cl_som_am57x_cpsw_slaves, 48 .ale_reg_ofs = 0xd00, 49 .ale_entries = 1024, 50 .host_port_reg_ofs = 0x108, 51 .hw_stats_reg_ofs = 0x900, 52 .bd_ram_ofs = 0x2000, 53 .mac_control = (1 << 5), 54 .control = cpsw_control, 55 .host_port_num = 0, 56 .version = CPSW_CTRL_VERSION_2, 57 }; 58 59 /* 60 * cl_som_am57x_efuse_read_mac_addr() - read Ethernet port MAC address. 61 * The information is retrieved from the SOC's registers. 62 * @buff: read buffer. 63 * @port_num: port number. 64 */ 65 static void cl_som_am57x_efuse_read_mac_addr(uchar *buff, uint port_num) 66 { 67 uint32_t mac_hi, mac_lo; 68 69 if (port_num) { 70 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 71 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 72 } else { 73 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 74 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 75 } 76 77 buff[0] = (mac_hi & 0xFF0000) >> 16; 78 buff[1] = (mac_hi & 0xFF00) >> 8; 79 buff[2] = mac_hi & 0xFF; 80 buff[3] = (mac_lo & 0xFF0000) >> 16; 81 buff[4] = (mac_lo & 0xFF00) >> 8; 82 buff[5] = mac_lo & 0xFF; 83 } 84 85 /* 86 * cl_som_am57x_handle_mac_address() - set MAC address in the U-Boot 87 * environment. 88 * The address is retrieved retrieved from an EEPROM field or from the 89 * SOC's registers. 90 * @env_name: U-Boot environment name. 91 * @field_name: EEPROM field name. 92 * @port_num: SOC's port number. 93 */ 94 static int cl_som_am57x_handle_mac_address(char *env_name, uint port_num) 95 { 96 int ret; 97 uint8_t enetaddr[6]; 98 99 ret = eth_env_get_enetaddr(env_name, enetaddr); 100 if (ret) 101 return 0; 102 103 ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); 104 105 if (ret || !is_valid_ethaddr(enetaddr)) 106 cl_som_am57x_efuse_read_mac_addr(enetaddr, port_num); 107 108 if (!is_valid_ethaddr(enetaddr)) 109 return -1; 110 111 ret = eth_env_set_enetaddr(env_name, enetaddr); 112 if (ret) 113 printf("cl-som-am57x: Failed to set Eth port %d MAC address\n", 114 port_num); 115 116 return ret; 117 } 118 119 #define CL_SOM_AM57X_PHY_ADDR2 0x01 120 #define AR8033_PHY_DEBUG_ADDR_REG 0x1d 121 #define AR8033_PHY_DEBUG_DATA_REG 0x1e 122 #define AR8033_DEBUG_RGMII_RX_CLK_DLY_REG 0x00 123 #define AR8033_DEBUG_RGMII_TX_CLK_DLY_REG 0x05 124 #define AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK (1 << 15) 125 #define AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK (1 << 8) 126 127 /* 128 * cl_som_am57x_rgmii_clk_delay() - Set RGMII clock delay. 129 * Enable RX delay, disable TX delay. 130 */ 131 static void cl_som_am57x_rgmii_clk_delay(void) 132 { 133 uint16_t mii_reg_val; 134 const char *devname; 135 136 devname = miiphy_get_current_dev(); 137 /* PHY 2 */ 138 miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG, 139 AR8033_DEBUG_RGMII_RX_CLK_DLY_REG); 140 miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, 141 &mii_reg_val); 142 mii_reg_val |= AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK; 143 miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, 144 mii_reg_val); 145 146 miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG, 147 AR8033_DEBUG_RGMII_TX_CLK_DLY_REG); 148 miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, 149 &mii_reg_val); 150 mii_reg_val &= ~AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK; 151 miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, 152 mii_reg_val); 153 } 154 155 #define CL_SOM_AM57X_GPIO_PHY1_RST 92 /* GPIO3_28 */ 156 #define CL_SOM_AM57X_RGMII_PORT1 1 157 158 int board_eth_init(bd_t *bis) 159 { 160 int ret; 161 uint32_t ctrl_val; 162 char *cpsw_phy_envval; 163 int cpsw_act_phy = 1; 164 165 /* SB-SOM-AM57x primary Eth (P21) is routed to RGMII1 */ 166 ret = cl_som_am57x_handle_mac_address("ethaddr", 167 CL_SOM_AM57X_RGMII_PORT1); 168 169 if (ret) 170 return -1; 171 172 /* Select RGMII for GMII1_SEL */ 173 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 174 ctrl_val |= 0x22; 175 writel(ctrl_val, (*ctrl)->control_core_control_io1); 176 mdelay(10); 177 178 gpio_request(CL_SOM_AM57X_GPIO_PHY1_RST, "phy1_rst"); 179 gpio_direction_output(CL_SOM_AM57X_GPIO_PHY1_RST, 0); 180 mdelay(20); 181 182 gpio_set_value(CL_SOM_AM57X_GPIO_PHY1_RST, 1); 183 mdelay(20); 184 185 cpsw_phy_envval = env_get("cpsw_phy"); 186 if (cpsw_phy_envval != NULL) 187 cpsw_act_phy = simple_strtoul(cpsw_phy_envval, NULL, 0); 188 189 cl_som_am57_cpsw_data.active_slave = cpsw_act_phy; 190 191 ret = cpsw_register(&cl_som_am57_cpsw_data); 192 if (ret < 0) 193 printf("Error %d registering CPSW switch\n", ret); 194 195 /* Set RGMII clock delay */ 196 cl_som_am57x_rgmii_clk_delay(); 197 198 return ret; 199 } 200