xref: /openbmc/u-boot/board/compal/paz00/paz00.c (revision dd1033e4)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  */
8 
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/tegra.h>
12 #include <asm/arch/pinmux.h>
13 #include <asm/gpio.h>
14 
15 #ifdef CONFIG_MMC_SDHCI_TEGRA
16 /*
17  * Routine: pin_mux_mmc
18  * Description: setup the pin muxes/tristate values for the SDMMC(s)
19  */
20 void pin_mux_mmc(void)
21 {
22 	/* SDMMC4: config 3, x8 on 2nd set of pins */
23 	pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
24 	pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
25 	pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
26 
27 	pinmux_tristate_disable(PMUX_PINGRP_ATB);
28 	pinmux_tristate_disable(PMUX_PINGRP_GMA);
29 	pinmux_tristate_disable(PMUX_PINGRP_GME);
30 
31 	/* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
32 	pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
33 
34 	pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
35 
36 	/* For power GPIO PV1 */
37 	pinmux_tristate_disable(PMUX_PINGRP_UAC);
38 	/* For CD GPIO PV5 */
39 	pinmux_tristate_disable(PMUX_PINGRP_GPV);
40 }
41 #endif
42 
43 #ifdef CONFIG_DM_VIDEO
44 /* this is a weak define that we are overriding */
45 void pin_mux_display(void)
46 {
47 	debug("init display pinmux\n");
48 
49 	/* EN_VDD_PANEL GPIO A4 */
50 	pinmux_tristate_disable(PMUX_PINGRP_DAP2);
51 }
52 #endif
53