1 /* 2 * Copyright (C) 2012 3 * David Purdy <david.c.purdy@gmail.com> 4 * 5 * Based on Kirkwood support: 6 * (C) Copyright 2009 7 * Marvell Semiconductor <www.marvell.com> 8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; If not, see <http://www.gnu.org/licenses/>. 25 */ 26 27 #include <common.h> 28 #include <miiphy.h> 29 #include <asm/arch/cpu.h> 30 #include <asm/arch/kirkwood.h> 31 #include <asm/arch/mpp.h> 32 #include "pogo_e02.h" 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 int board_early_init_f(void) 37 { 38 /* 39 * default gpio configuration 40 * There are maximum 64 gpios controlled through 2 sets of registers 41 * the below configuration configures mainly initial LED status 42 */ 43 kw_config_gpio(POGO_E02_OE_VAL_LOW, 44 POGO_E02_OE_VAL_HIGH, 45 POGO_E02_OE_LOW, POGO_E02_OE_HIGH); 46 47 /* Multi-Purpose Pins Functionality configuration */ 48 u32 kwmpp_config[] = { 49 MPP0_NF_IO2, 50 MPP1_NF_IO3, 51 MPP2_NF_IO4, 52 MPP3_NF_IO5, 53 MPP4_NF_IO6, 54 MPP5_NF_IO7, 55 MPP6_SYSRST_OUTn, 56 MPP7_GPO, 57 MPP8_UART0_RTS, 58 MPP9_UART0_CTS, 59 MPP10_UART0_TXD, 60 MPP11_UART0_RXD, 61 MPP12_SD_CLK, 62 MPP13_SD_CMD, 63 MPP14_SD_D0, 64 MPP15_SD_D1, 65 MPP16_SD_D2, 66 MPP17_SD_D3, 67 MPP18_NF_IO0, 68 MPP19_NF_IO1, 69 MPP29_TSMP9, /* USB Power Enable */ 70 MPP48_GPIO, /* LED green */ 71 MPP49_GPIO, /* LED orange */ 72 0 73 }; 74 kirkwood_mpp_conf(kwmpp_config); 75 return 0; 76 } 77 78 int board_init(void) 79 { 80 /* Boot parameters address */ 81 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 82 83 return 0; 84 } 85 86 #ifdef CONFIG_RESET_PHY_R 87 /* Configure and initialize PHY */ 88 void reset_phy(void) 89 { 90 u16 reg; 91 u16 devadr; 92 char *name = "egiga0"; 93 94 if (miiphy_set_current_dev(name)) 95 return; 96 97 /* command to read PHY dev address */ 98 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { 99 printf("Err..(%s) could not read PHY dev address\n", __func__); 100 return; 101 } 102 103 /* 104 * Enable RGMII delay on Tx and Rx for CPU port 105 * Ref: sec 4.7.2 of chip datasheet 106 */ 107 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); 108 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); 109 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); 110 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); 111 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); 112 113 /* reset the phy */ 114 miiphy_reset(name, devadr); 115 116 debug("88E1116 Initialized on %s\n", name); 117 } 118 #endif /* CONFIG_RESET_PHY_R */ 119