1# 2# Copyright (C) 2012 3# David Purdy <david.c.purdy@gmail.com> 4# 5# Based on Kirkwood support: 6# (C) Copyright 2009 7# Marvell Semiconductor <www.marvell.com> 8# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com> 9# 10# See file CREDITS for list of people who contributed to this 11# project. 12# 13# This program is free software; you can redistribute it and/or 14# modify it under the terms of the GNU General Public License as 15# published by the Free Software Foundation; either version 2 of 16# the License, or (at your option) any later version. 17# 18# This program is distributed in the hope that it will be useful, 19# but WITHOUT ANY WARRANTY; without even the implied warranty of 20# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21# GNU General Public License for more details. 22# 23# You should have received a copy of the GNU General Public License 24# along with this program; If not, see <http://www.gnu.org/licenses/>. 25# 26# Refer docs/README.kwimage for more details about how-to configure 27# and create kirkwood boot image 28# 29 30# Boot Media configurations 31BOOT_FROM nand 32NAND_ECC_MODE default 33NAND_PAGE_SIZE 0x0800 34 35# SOC registers configuration using bootrom header extension 36# Maximum KWBIMAGE_MAX_CONFIG configurations allowed 37 38# Configure RGMII-0 interface pad voltage to 1.8V 39DATA 0xffd100e0 0x1b1b1b9b 40 41#Dram initalization for SINGLE x16 CL=5 @ 400MHz 42DATA 0xffd01400 0x43000c30 # DDR Configuration register 43# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 44# bit23-14: zero 45# bit24: 1= enable exit self refresh mode on DDR access 46# bit25: 1 required 47# bit29-26: zero 48# bit31-30: 01 49 50DATA 0xffd01404 0x37543000 # DDR Controller Control Low 51# bit 4: 0=addr/cmd in smame cycle 52# bit 5: 0=clk is driven during self refresh, we don't care for APX 53# bit 6: 0=use recommended falling edge of clk for addr/cmd 54# bit14: 0=input buffer always powered up 55# bit18: 1=cpu lock transaction enabled 56# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 57# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM 58# bit30-28: 3 required 59# bit31: 0=no additional STARTBURST delay 60 61DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) 62# bit3-0: TRAS lsbs 63# bit7-4: TRCD 64# bit11- 8: TRP 65# bit15-12: TWR 66# bit19-16: TWTR 67# bit20: TRAS msb 68# bit23-21: 0x0 69# bit27-24: TRRD 70# bit31-28: TRTP 71 72DATA 0xffd0140c 0x00000a33 # DDR Timing (High) 73# bit6-0: TRFC 74# bit8-7: TR2R 75# bit10-9: TR2W 76# bit12-11: TW2W 77# bit31-13: zero required 78 79DATA 0xffd01410 0x000000cc # DDR Address Control 80# bit1-0: 00, Cs0width=x8 81# bit3-2: 11, Cs0size=1Gb 82# bit5-4: 00, Cs1width=x8 83# bit7-6: 11, Cs1size=1Gb 84# bit9-8: 00, Cs2width=nonexistent 85# bit11-10: 00, Cs2size =nonexistent 86# bit13-12: 00, Cs3width=nonexistent 87# bit15-14: 00, Cs3size =nonexistent 88# bit16: 0, Cs0AddrSel 89# bit17: 0, Cs1AddrSel 90# bit18: 0, Cs2AddrSel 91# bit19: 0, Cs3AddrSel 92# bit31-20: 0 required 93 94DATA 0xffd01414 0x00000000 # DDR Open Pages Control 95# bit0: 0, OpenPage enabled 96# bit31-1: 0 required 97 98DATA 0xffd01418 0x00000000 # DDR Operation 99# bit3-0: 0x0, DDR cmd 100# bit31-4: 0 required 101 102DATA 0xffd0141c 0x00000c52 # DDR Mode 103# bit2-0: 2, BurstLen=2 required 104# bit3: 0, BurstType=0 required 105# bit6-4: 4, CL=5 106# bit7: 0, TestMode=0 normal 107# bit8: 0, DLL reset=0 normal 108# bit11-9: 6, auto-precharge write recovery ???????????? 109# bit12: 0, PD must be zero 110# bit31-13: 0 required 111 112DATA 0xffd01420 0x00000040 # DDR Extended Mode 113# bit0: 0, DDR DLL enabled 114# bit1: 0, DDR drive strenght normal 115# bit2: 0, DDR ODT control lsd (disabled) 116# bit5-3: 000, required 117# bit6: 1, DDR ODT control msb, (disabled) 118# bit9-7: 000, required 119# bit10: 0, differential DQS enabled 120# bit11: 0, required 121# bit12: 0, DDR output buffer enabled 122# bit31-13: 0 required 123 124DATA 0xffd01424 0x0000f17f # DDR Controller Control High 125# bit2-0: 111, required 126# bit3 : 1 , MBUS Burst Chop disabled 127# bit6-4: 111, required 128# bit7 : 0 129# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz 130# bit9 : 0 , no half clock cycle addition to dataout 131# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals 132# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh 133# bit15-12: 1111 required 134# bit31-16: 0 required 135 136DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) 137DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) 138 139DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 140DATA 0xffd01504 0x0ffffff1 # CS[0]n Size 141# bit0: 1, Window enabled 142# bit1: 0, Write Protect disabled 143# bit3-2: 00, CS0 hit selected 144# bit23-4: ones, required 145# bit31-24: 0x0F, Size (i.e. 256MB) 146 147DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb 148DATA 0xffd0150c 0x00000000 # CS[2]n Size, window disabled 149 150DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled 151DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled 152 153DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) 154# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 155# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 156# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 157# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 158 159DATA 0xffd01498 0x00000000 # DDR ODT Control (High) 160# bit1-0: 00, ODT0 controlled by ODT Control (low) register above 161# bit3-2: 01, ODT1 active NEVER! 162# bit31-4: zero, required 163 164DATA 0xffd0149c 0x0000e803 # CPU ODT Control 165DATA 0xffd01480 0x00000001 # DDR Initialization Control 166#bit0=1, enable DDR init upon this register write 167 168# End of Header extension 169DATA 0x0 0x0 170