1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2a7f480d9SStefan Roese /* 3a7f480d9SStefan Roese * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 4a7f480d9SStefan Roese */ 5a7f480d9SStefan Roese 6a7f480d9SStefan Roese #include <asm/arch/clock.h> 7a7f480d9SStefan Roese #include <asm/arch/iomux.h> 8a7f480d9SStefan Roese #include <asm/arch/imx-regs.h> 9a7f480d9SStefan Roese #include <asm/arch/crm_regs.h> 10a7f480d9SStefan Roese #include <asm/arch/mx6ul_pins.h> 11a7f480d9SStefan Roese #include <asm/arch/mx6-pins.h> 12a7f480d9SStefan Roese #include <asm/arch/sys_proto.h> 13a7f480d9SStefan Roese #include <asm/gpio.h> 14552a848eSStefano Babic #include <asm/mach-imx/iomux-v3.h> 15552a848eSStefano Babic #include <asm/mach-imx/boot_mode.h> 16552a848eSStefano Babic #include <asm/mach-imx/mxc_i2c.h> 17a7f480d9SStefan Roese #include <asm/io.h> 18a7f480d9SStefan Roese #include <common.h> 19a7f480d9SStefan Roese #include <fsl_esdhc.h> 20a7f480d9SStefan Roese #include <i2c.h> 21a7f480d9SStefan Roese #include <miiphy.h> 22a7f480d9SStefan Roese #include <mmc.h> 23a7f480d9SStefan Roese #include <netdev.h> 24a7f480d9SStefan Roese #include <usb.h> 25ff6552e8STom Rini #include <usb/ehci-ci.h> 26a7f480d9SStefan Roese 27a7f480d9SStefan Roese DECLARE_GLOBAL_DATA_PTR; 28a7f480d9SStefan Roese 29a7f480d9SStefan Roese #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 30a7f480d9SStefan Roese PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 31a7f480d9SStefan Roese PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 32a7f480d9SStefan Roese 33a7f480d9SStefan Roese #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 34a7f480d9SStefan Roese PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 35a7f480d9SStefan Roese PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 36a7f480d9SStefan Roese 37a7f480d9SStefan Roese #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 38a7f480d9SStefan Roese PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 39a7f480d9SStefan Roese PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 40a7f480d9SStefan Roese PAD_CTL_ODE) 41a7f480d9SStefan Roese 42a7f480d9SStefan Roese #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 43a7f480d9SStefan Roese PAD_CTL_SPEED_HIGH | \ 44a7f480d9SStefan Roese PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 45a7f480d9SStefan Roese 46a7f480d9SStefan Roese #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 47a7f480d9SStefan Roese PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) 48a7f480d9SStefan Roese 49a7f480d9SStefan Roese #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 50a7f480d9SStefan Roese 51a7f480d9SStefan Roese #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 52a7f480d9SStefan Roese PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) 53a7f480d9SStefan Roese 54a7f480d9SStefan Roese #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 55a7f480d9SStefan Roese PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 56a7f480d9SStefan Roese PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ 57a7f480d9SStefan Roese PAD_CTL_SRE_FAST) 58a7f480d9SStefan Roese 59a7f480d9SStefan Roese #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 60a7f480d9SStefan Roese 61a7f480d9SStefan Roese static struct i2c_pads_info i2c_pad_info1 = { 62a7f480d9SStefan Roese .scl = { 63a7f480d9SStefan Roese .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, 64a7f480d9SStefan Roese .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, 65a7f480d9SStefan Roese .gp = IMX_GPIO_NR(1, 2), 66a7f480d9SStefan Roese }, 67a7f480d9SStefan Roese .sda = { 68a7f480d9SStefan Roese .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, 69a7f480d9SStefan Roese .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, 70a7f480d9SStefan Roese .gp = IMX_GPIO_NR(1, 3), 71a7f480d9SStefan Roese }, 72a7f480d9SStefan Roese }; 73a7f480d9SStefan Roese 74a7f480d9SStefan Roese static struct i2c_pads_info i2c_pad_info2 = { 75a7f480d9SStefan Roese .scl = { 76a7f480d9SStefan Roese .i2c_mode = MX6_PAD_GPIO1_IO00__I2C2_SCL | PC, 77a7f480d9SStefan Roese .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC, 78a7f480d9SStefan Roese .gp = IMX_GPIO_NR(1, 0), 79a7f480d9SStefan Roese }, 80a7f480d9SStefan Roese .sda = { 81a7f480d9SStefan Roese .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC, 82a7f480d9SStefan Roese .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC, 83a7f480d9SStefan Roese .gp = IMX_GPIO_NR(1, 1), 84a7f480d9SStefan Roese }, 85a7f480d9SStefan Roese }; 86a7f480d9SStefan Roese 87a7f480d9SStefan Roese static struct i2c_pads_info i2c_pad_info4 = { 88a7f480d9SStefan Roese .scl = { 89a7f480d9SStefan Roese .i2c_mode = MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC, 90a7f480d9SStefan Roese .gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC, 91a7f480d9SStefan Roese .gp = IMX_GPIO_NR(1, 20), 92a7f480d9SStefan Roese }, 93a7f480d9SStefan Roese .sda = { 94a7f480d9SStefan Roese .i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC, 95a7f480d9SStefan Roese .gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC, 96a7f480d9SStefan Roese .gp = IMX_GPIO_NR(1, 21), 97a7f480d9SStefan Roese }, 98a7f480d9SStefan Roese }; 99a7f480d9SStefan Roese 100a7f480d9SStefan Roese int dram_init(void) 101a7f480d9SStefan Roese { 102a7f480d9SStefan Roese gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 103a7f480d9SStefan Roese 104a7f480d9SStefan Roese return 0; 105a7f480d9SStefan Roese } 106a7f480d9SStefan Roese 107a7f480d9SStefan Roese static iomux_v3_cfg_t const uart1_pads[] = { 108a7f480d9SStefan Roese MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 109a7f480d9SStefan Roese MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 110fe12386cSAnatolij Gustschin MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), 111fe12386cSAnatolij Gustschin MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), 112a7f480d9SStefan Roese }; 113a7f480d9SStefan Roese 114a7f480d9SStefan Roese static iomux_v3_cfg_t const uart4_pads[] = { 115a7f480d9SStefan Roese MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 116a7f480d9SStefan Roese MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 117a7f480d9SStefan Roese }; 118a7f480d9SStefan Roese 119a7f480d9SStefan Roese static iomux_v3_cfg_t const uart5_pads[] = { 120a7f480d9SStefan Roese MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 121a7f480d9SStefan Roese MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 122a7f480d9SStefan Roese MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), 123a7f480d9SStefan Roese MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), 124a7f480d9SStefan Roese }; 125a7f480d9SStefan Roese 126fe12386cSAnatolij Gustschin static iomux_v3_cfg_t const uart7_pads[] = { 127fe12386cSAnatolij Gustschin MX6_PAD_ENET2_RX_EN__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 128fe12386cSAnatolij Gustschin MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 129fe12386cSAnatolij Gustschin }; 130fe12386cSAnatolij Gustschin 131a7f480d9SStefan Roese static iomux_v3_cfg_t const uart8_pads[] = { 132fe12386cSAnatolij Gustschin MX6_PAD_LCD_DATA20__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 133fe12386cSAnatolij Gustschin MX6_PAD_LCD_DATA21__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 134a7f480d9SStefan Roese }; 135a7f480d9SStefan Roese 136a7f480d9SStefan Roese static void setup_iomux_uart(void) 137a7f480d9SStefan Roese { 138a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 139a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 140a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); 141fe12386cSAnatolij Gustschin imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads)); 142a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads)); 143a7f480d9SStefan Roese } 144a7f480d9SStefan Roese 145a7f480d9SStefan Roese /* eMMC on USDHC2 */ 146a7f480d9SStefan Roese static iomux_v3_cfg_t const usdhc2_pads[] = { 147a7f480d9SStefan Roese MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 148a7f480d9SStefan Roese MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 149a7f480d9SStefan Roese MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 150a7f480d9SStefan Roese MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 151a7f480d9SStefan Roese MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 152a7f480d9SStefan Roese MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 153a7f480d9SStefan Roese MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 154a7f480d9SStefan Roese MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 155a7f480d9SStefan Roese MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 156a7f480d9SStefan Roese MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 157a7f480d9SStefan Roese 158a7f480d9SStefan Roese /* 159a7f480d9SStefan Roese * RST_B 160a7f480d9SStefan Roese */ 161a7f480d9SStefan Roese MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL), 162a7f480d9SStefan Roese }; 163a7f480d9SStefan Roese 164a7f480d9SStefan Roese static struct fsl_esdhc_cfg usdhc_cfg = { 165a7f480d9SStefan Roese .esdhc_base = USDHC2_BASE_ADDR, 166a7f480d9SStefan Roese .max_bus_width = 8, 167a7f480d9SStefan Roese }; 168a7f480d9SStefan Roese 169a7f480d9SStefan Roese #define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9) 170a7f480d9SStefan Roese 171a7f480d9SStefan Roese int board_mmc_getcd(struct mmc *mmc) 172a7f480d9SStefan Roese { 173a7f480d9SStefan Roese /* eMMC is always present */ 174a7f480d9SStefan Roese return 1; 175a7f480d9SStefan Roese } 176a7f480d9SStefan Roese 177a7f480d9SStefan Roese int board_mmc_init(bd_t *bis) 178a7f480d9SStefan Roese { 179a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 180a7f480d9SStefan Roese 181a7f480d9SStefan Roese usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 182a7f480d9SStefan Roese 183a7f480d9SStefan Roese return fsl_esdhc_initialize(bis, &usdhc_cfg); 184a7f480d9SStefan Roese } 185a7f480d9SStefan Roese 186a7f480d9SStefan Roese #define USB_OTHERREGS_OFFSET 0x800 187a7f480d9SStefan Roese #define UCTRL_PWR_POL (1 << 9) 188a7f480d9SStefan Roese 189a7f480d9SStefan Roese static iomux_v3_cfg_t const usb_otg_pads[] = { 190a7f480d9SStefan Roese /* OTG1 */ 191a7f480d9SStefan Roese MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 192a7f480d9SStefan Roese MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), 193a7f480d9SStefan Roese /* OTG2 */ 194a7f480d9SStefan Roese MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 195a7f480d9SStefan Roese MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), 196a7f480d9SStefan Roese }; 197a7f480d9SStefan Roese 198a7f480d9SStefan Roese static void setup_usb(void) 199a7f480d9SStefan Roese { 200a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 201a7f480d9SStefan Roese ARRAY_SIZE(usb_otg_pads)); 202a7f480d9SStefan Roese } 203a7f480d9SStefan Roese 204a7f480d9SStefan Roese int board_usb_phy_mode(int port) 205a7f480d9SStefan Roese { 206a7f480d9SStefan Roese if (port == 1) 207a7f480d9SStefan Roese return USB_INIT_HOST; 208a7f480d9SStefan Roese else 209a7f480d9SStefan Roese return usb_phy_mode(port); 210a7f480d9SStefan Roese } 211a7f480d9SStefan Roese 212a7f480d9SStefan Roese int board_ehci_hcd_init(int port) 213a7f480d9SStefan Roese { 214a7f480d9SStefan Roese u32 *usbnc_usb_ctrl; 215a7f480d9SStefan Roese 216a7f480d9SStefan Roese if (port > 1) 217a7f480d9SStefan Roese return -EINVAL; 218a7f480d9SStefan Roese 219a7f480d9SStefan Roese usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 220a7f480d9SStefan Roese port * 4); 221a7f480d9SStefan Roese 222a7f480d9SStefan Roese /* Set Power polarity */ 223a7f480d9SStefan Roese setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 224a7f480d9SStefan Roese 225a7f480d9SStefan Roese return 0; 226a7f480d9SStefan Roese } 227a7f480d9SStefan Roese 228a7f480d9SStefan Roese static iomux_v3_cfg_t const fec1_pads[] = { 229a7f480d9SStefan Roese MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 230a7f480d9SStefan Roese MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 231a7f480d9SStefan Roese MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 232a7f480d9SStefan Roese MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 233a7f480d9SStefan Roese MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 234a7f480d9SStefan Roese MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 235a7f480d9SStefan Roese MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 236a7f480d9SStefan Roese MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 237a7f480d9SStefan Roese MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 238a7f480d9SStefan Roese MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 239a7f480d9SStefan Roese 240a7f480d9SStefan Roese /* ENET1 reset */ 241a7f480d9SStefan Roese MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), 242a7f480d9SStefan Roese /* ENET1 interrupt */ 243a7f480d9SStefan Roese MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), 244a7f480d9SStefan Roese }; 245a7f480d9SStefan Roese 246a7f480d9SStefan Roese #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17) 247a7f480d9SStefan Roese 248a7f480d9SStefan Roese int board_eth_init(bd_t *bis) 249a7f480d9SStefan Roese { 250a7f480d9SStefan Roese int ret; 251a7f480d9SStefan Roese 252a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 253a7f480d9SStefan Roese 254a7f480d9SStefan Roese /* Reset LAN8742 PHY */ 255a7f480d9SStefan Roese ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset"); 256a7f480d9SStefan Roese if (!ret) 257a7f480d9SStefan Roese gpio_direction_output(ENET_PHY_RESET_GPIO , 0); 258a7f480d9SStefan Roese mdelay(10); 259a7f480d9SStefan Roese gpio_set_value(ENET_PHY_RESET_GPIO, 1); 260a7f480d9SStefan Roese mdelay(10); 261a7f480d9SStefan Roese 262a7f480d9SStefan Roese return cpu_eth_init(bis); 263a7f480d9SStefan Roese } 264a7f480d9SStefan Roese 265a7f480d9SStefan Roese static int setup_fec(int fec_id) 266a7f480d9SStefan Roese { 267a7f480d9SStefan Roese struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 268a7f480d9SStefan Roese int ret; 269a7f480d9SStefan Roese 270a7f480d9SStefan Roese /* 271a7f480d9SStefan Roese * Use 50M anatop loopback REF_CLK1 for ENET1, 272a7f480d9SStefan Roese * clear gpr1[13], set gpr1[17]. 273a7f480d9SStefan Roese */ 274a7f480d9SStefan Roese clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 275a7f480d9SStefan Roese IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); 276a7f480d9SStefan Roese 277a7f480d9SStefan Roese ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); 278a7f480d9SStefan Roese if (ret) 279a7f480d9SStefan Roese return ret; 280a7f480d9SStefan Roese 281a7f480d9SStefan Roese enable_enet_clk(1); 282a7f480d9SStefan Roese 283a7f480d9SStefan Roese return 0; 284a7f480d9SStefan Roese } 285a7f480d9SStefan Roese 286a7f480d9SStefan Roese int board_phy_config(struct phy_device *phydev) 287a7f480d9SStefan Roese { 288a7f480d9SStefan Roese if (phydev->drv->config) 289a7f480d9SStefan Roese phydev->drv->config(phydev); 290a7f480d9SStefan Roese 291a7f480d9SStefan Roese return 0; 292a7f480d9SStefan Roese } 293a7f480d9SStefan Roese 294a7f480d9SStefan Roese int board_early_init_f(void) 295a7f480d9SStefan Roese { 296a7f480d9SStefan Roese setup_iomux_uart(); 297a7f480d9SStefan Roese 298a7f480d9SStefan Roese return 0; 299a7f480d9SStefan Roese } 300a7f480d9SStefan Roese 301a7f480d9SStefan Roese int board_init(void) 302a7f480d9SStefan Roese { 303a7f480d9SStefan Roese /* Address of boot parameters */ 304a7f480d9SStefan Roese gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 305a7f480d9SStefan Roese 306a7f480d9SStefan Roese setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 307a7f480d9SStefan Roese setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 308a7f480d9SStefan Roese setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); 309a7f480d9SStefan Roese 310a7f480d9SStefan Roese setup_fec(CONFIG_FEC_ENET_DEV); 311a7f480d9SStefan Roese 312a7f480d9SStefan Roese setup_usb(); 313a7f480d9SStefan Roese 314a7f480d9SStefan Roese return 0; 315a7f480d9SStefan Roese } 316a7f480d9SStefan Roese 317a7f480d9SStefan Roese static const struct boot_mode board_boot_modes[] = { 318a7f480d9SStefan Roese /* 8 bit bus width */ 319a7f480d9SStefan Roese {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)}, 320a7f480d9SStefan Roese { NULL, 0 }, 321a7f480d9SStefan Roese }; 322a7f480d9SStefan Roese 323a7f480d9SStefan Roese int board_late_init(void) 324a7f480d9SStefan Roese { 325a7f480d9SStefan Roese add_board_boot_modes(board_boot_modes); 326382bee57SSimon Glass env_set("board_name", "xpress"); 327a7f480d9SStefan Roese 328a7f480d9SStefan Roese return 0; 329a7f480d9SStefan Roese } 330a7f480d9SStefan Roese 331a7f480d9SStefan Roese int checkboard(void) 332a7f480d9SStefan Roese { 333a7f480d9SStefan Roese puts("Board: CCV-EVA xPress\n"); 334a7f480d9SStefan Roese 335a7f480d9SStefan Roese return 0; 336a7f480d9SStefan Roese } 337