1a7f480d9SStefan Roese /* 2a7f480d9SStefan Roese * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 3a7f480d9SStefan Roese * 4a7f480d9SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5a7f480d9SStefan Roese */ 6a7f480d9SStefan Roese 7a7f480d9SStefan Roese #include <asm/arch/clock.h> 8a7f480d9SStefan Roese #include <asm/arch/iomux.h> 9a7f480d9SStefan Roese #include <asm/arch/imx-regs.h> 10a7f480d9SStefan Roese #include <asm/arch/crm_regs.h> 11a7f480d9SStefan Roese #include <asm/arch/mx6ul_pins.h> 12a7f480d9SStefan Roese #include <asm/arch/mx6-pins.h> 13a7f480d9SStefan Roese #include <asm/arch/sys_proto.h> 14a7f480d9SStefan Roese #include <asm/gpio.h> 15552a848eSStefano Babic #include <asm/mach-imx/iomux-v3.h> 16552a848eSStefano Babic #include <asm/mach-imx/boot_mode.h> 17552a848eSStefano Babic #include <asm/mach-imx/mxc_i2c.h> 18a7f480d9SStefan Roese #include <asm/io.h> 19a7f480d9SStefan Roese #include <common.h> 20a7f480d9SStefan Roese #include <fsl_esdhc.h> 21a7f480d9SStefan Roese #include <i2c.h> 22a7f480d9SStefan Roese #include <miiphy.h> 23a7f480d9SStefan Roese #include <mmc.h> 24a7f480d9SStefan Roese #include <netdev.h> 25a7f480d9SStefan Roese #include <usb.h> 26ff6552e8STom Rini #include <usb/ehci-ci.h> 27a7f480d9SStefan Roese 28a7f480d9SStefan Roese DECLARE_GLOBAL_DATA_PTR; 29a7f480d9SStefan Roese 30a7f480d9SStefan Roese #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 31a7f480d9SStefan Roese PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 32a7f480d9SStefan Roese PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 33a7f480d9SStefan Roese 34a7f480d9SStefan Roese #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 35a7f480d9SStefan Roese PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 36a7f480d9SStefan Roese PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 37a7f480d9SStefan Roese 38a7f480d9SStefan Roese #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 39a7f480d9SStefan Roese PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 40a7f480d9SStefan Roese PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 41a7f480d9SStefan Roese PAD_CTL_ODE) 42a7f480d9SStefan Roese 43a7f480d9SStefan Roese #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 44a7f480d9SStefan Roese PAD_CTL_SPEED_HIGH | \ 45a7f480d9SStefan Roese PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 46a7f480d9SStefan Roese 47a7f480d9SStefan Roese #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 48a7f480d9SStefan Roese PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) 49a7f480d9SStefan Roese 50a7f480d9SStefan Roese #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 51a7f480d9SStefan Roese 52a7f480d9SStefan Roese #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 53a7f480d9SStefan Roese PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) 54a7f480d9SStefan Roese 55a7f480d9SStefan Roese #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 56a7f480d9SStefan Roese PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 57a7f480d9SStefan Roese PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ 58a7f480d9SStefan Roese PAD_CTL_SRE_FAST) 59a7f480d9SStefan Roese 60a7f480d9SStefan Roese #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 61a7f480d9SStefan Roese 62a7f480d9SStefan Roese static struct i2c_pads_info i2c_pad_info1 = { 63a7f480d9SStefan Roese .scl = { 64a7f480d9SStefan Roese .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, 65a7f480d9SStefan Roese .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, 66a7f480d9SStefan Roese .gp = IMX_GPIO_NR(1, 2), 67a7f480d9SStefan Roese }, 68a7f480d9SStefan Roese .sda = { 69a7f480d9SStefan Roese .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, 70a7f480d9SStefan Roese .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, 71a7f480d9SStefan Roese .gp = IMX_GPIO_NR(1, 3), 72a7f480d9SStefan Roese }, 73a7f480d9SStefan Roese }; 74a7f480d9SStefan Roese 75a7f480d9SStefan Roese static struct i2c_pads_info i2c_pad_info2 = { 76a7f480d9SStefan Roese .scl = { 77a7f480d9SStefan Roese .i2c_mode = MX6_PAD_GPIO1_IO00__I2C2_SCL | PC, 78a7f480d9SStefan Roese .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO00 | PC, 79a7f480d9SStefan Roese .gp = IMX_GPIO_NR(1, 0), 80a7f480d9SStefan Roese }, 81a7f480d9SStefan Roese .sda = { 82a7f480d9SStefan Roese .i2c_mode = MX6_PAD_GPIO1_IO01__I2C2_SDA | PC, 83a7f480d9SStefan Roese .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO01 | PC, 84a7f480d9SStefan Roese .gp = IMX_GPIO_NR(1, 1), 85a7f480d9SStefan Roese }, 86a7f480d9SStefan Roese }; 87a7f480d9SStefan Roese 88a7f480d9SStefan Roese static struct i2c_pads_info i2c_pad_info4 = { 89a7f480d9SStefan Roese .scl = { 90a7f480d9SStefan Roese .i2c_mode = MX6_PAD_UART2_TX_DATA__I2C4_SCL | PC, 91a7f480d9SStefan Roese .gpio_mode = MX6_PAD_UART2_TX_DATA__GPIO1_IO20 | PC, 92a7f480d9SStefan Roese .gp = IMX_GPIO_NR(1, 20), 93a7f480d9SStefan Roese }, 94a7f480d9SStefan Roese .sda = { 95a7f480d9SStefan Roese .i2c_mode = MX6_PAD_UART2_RX_DATA__I2C4_SDA | PC, 96a7f480d9SStefan Roese .gpio_mode = MX6_PAD_UART2_RX_DATA__GPIO1_IO21 | PC, 97a7f480d9SStefan Roese .gp = IMX_GPIO_NR(1, 21), 98a7f480d9SStefan Roese }, 99a7f480d9SStefan Roese }; 100a7f480d9SStefan Roese 101a7f480d9SStefan Roese int dram_init(void) 102a7f480d9SStefan Roese { 103a7f480d9SStefan Roese gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 104a7f480d9SStefan Roese 105a7f480d9SStefan Roese return 0; 106a7f480d9SStefan Roese } 107a7f480d9SStefan Roese 108a7f480d9SStefan Roese static iomux_v3_cfg_t const uart1_pads[] = { 109a7f480d9SStefan Roese MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 110a7f480d9SStefan Roese MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 111a7f480d9SStefan Roese }; 112a7f480d9SStefan Roese 113a7f480d9SStefan Roese static iomux_v3_cfg_t const uart4_pads[] = { 114a7f480d9SStefan Roese MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 115a7f480d9SStefan Roese MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 116a7f480d9SStefan Roese }; 117a7f480d9SStefan Roese 118a7f480d9SStefan Roese static iomux_v3_cfg_t const uart5_pads[] = { 119a7f480d9SStefan Roese MX6_PAD_GPIO1_IO04__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 120a7f480d9SStefan Roese MX6_PAD_GPIO1_IO05__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 121a7f480d9SStefan Roese MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), 122a7f480d9SStefan Roese MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), 123a7f480d9SStefan Roese }; 124a7f480d9SStefan Roese 125a7f480d9SStefan Roese static iomux_v3_cfg_t const uart8_pads[] = { 126a7f480d9SStefan Roese MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 127a7f480d9SStefan Roese MX6_PAD_ENET2_TX_EN__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 128a7f480d9SStefan Roese MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), 129a7f480d9SStefan Roese MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), 130a7f480d9SStefan Roese }; 131a7f480d9SStefan Roese 132a7f480d9SStefan Roese static void setup_iomux_uart(void) 133a7f480d9SStefan Roese { 134a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 135a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 136a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); 137a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads)); 138a7f480d9SStefan Roese } 139a7f480d9SStefan Roese 140a7f480d9SStefan Roese /* eMMC on USDHC2 */ 141a7f480d9SStefan Roese static iomux_v3_cfg_t const usdhc2_pads[] = { 142a7f480d9SStefan Roese MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 143a7f480d9SStefan Roese MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 144a7f480d9SStefan Roese MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 145a7f480d9SStefan Roese MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 146a7f480d9SStefan Roese MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 147a7f480d9SStefan Roese MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 148a7f480d9SStefan Roese MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 149a7f480d9SStefan Roese MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 150a7f480d9SStefan Roese MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 151a7f480d9SStefan Roese MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 152a7f480d9SStefan Roese 153a7f480d9SStefan Roese /* 154a7f480d9SStefan Roese * RST_B 155a7f480d9SStefan Roese */ 156a7f480d9SStefan Roese MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL), 157a7f480d9SStefan Roese }; 158a7f480d9SStefan Roese 159a7f480d9SStefan Roese static struct fsl_esdhc_cfg usdhc_cfg = { 160a7f480d9SStefan Roese .esdhc_base = USDHC2_BASE_ADDR, 161a7f480d9SStefan Roese .max_bus_width = 8, 162a7f480d9SStefan Roese }; 163a7f480d9SStefan Roese 164a7f480d9SStefan Roese #define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9) 165a7f480d9SStefan Roese 166a7f480d9SStefan Roese int board_mmc_getcd(struct mmc *mmc) 167a7f480d9SStefan Roese { 168a7f480d9SStefan Roese /* eMMC is always present */ 169a7f480d9SStefan Roese return 1; 170a7f480d9SStefan Roese } 171a7f480d9SStefan Roese 172a7f480d9SStefan Roese int board_mmc_init(bd_t *bis) 173a7f480d9SStefan Roese { 174a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 175a7f480d9SStefan Roese 176a7f480d9SStefan Roese usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 177a7f480d9SStefan Roese 178a7f480d9SStefan Roese return fsl_esdhc_initialize(bis, &usdhc_cfg); 179a7f480d9SStefan Roese } 180a7f480d9SStefan Roese 181a7f480d9SStefan Roese #define USB_OTHERREGS_OFFSET 0x800 182a7f480d9SStefan Roese #define UCTRL_PWR_POL (1 << 9) 183a7f480d9SStefan Roese 184a7f480d9SStefan Roese static iomux_v3_cfg_t const usb_otg_pads[] = { 185a7f480d9SStefan Roese /* OTG1 */ 186a7f480d9SStefan Roese MX6_PAD_SD1_CMD__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 187a7f480d9SStefan Roese MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), 188a7f480d9SStefan Roese /* OTG2 */ 189a7f480d9SStefan Roese MX6_PAD_SD1_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 190a7f480d9SStefan Roese MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), 191a7f480d9SStefan Roese }; 192a7f480d9SStefan Roese 193a7f480d9SStefan Roese static void setup_usb(void) 194a7f480d9SStefan Roese { 195a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 196a7f480d9SStefan Roese ARRAY_SIZE(usb_otg_pads)); 197a7f480d9SStefan Roese } 198a7f480d9SStefan Roese 199a7f480d9SStefan Roese int board_usb_phy_mode(int port) 200a7f480d9SStefan Roese { 201a7f480d9SStefan Roese if (port == 1) 202a7f480d9SStefan Roese return USB_INIT_HOST; 203a7f480d9SStefan Roese else 204a7f480d9SStefan Roese return usb_phy_mode(port); 205a7f480d9SStefan Roese } 206a7f480d9SStefan Roese 207a7f480d9SStefan Roese int board_ehci_hcd_init(int port) 208a7f480d9SStefan Roese { 209a7f480d9SStefan Roese u32 *usbnc_usb_ctrl; 210a7f480d9SStefan Roese 211a7f480d9SStefan Roese if (port > 1) 212a7f480d9SStefan Roese return -EINVAL; 213a7f480d9SStefan Roese 214a7f480d9SStefan Roese usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 215a7f480d9SStefan Roese port * 4); 216a7f480d9SStefan Roese 217a7f480d9SStefan Roese /* Set Power polarity */ 218a7f480d9SStefan Roese setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 219a7f480d9SStefan Roese 220a7f480d9SStefan Roese return 0; 221a7f480d9SStefan Roese } 222a7f480d9SStefan Roese 223a7f480d9SStefan Roese static iomux_v3_cfg_t const fec1_pads[] = { 224a7f480d9SStefan Roese MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 225a7f480d9SStefan Roese MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 226a7f480d9SStefan Roese MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 227a7f480d9SStefan Roese MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 228a7f480d9SStefan Roese MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 229a7f480d9SStefan Roese MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 230a7f480d9SStefan Roese MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 231a7f480d9SStefan Roese MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 232a7f480d9SStefan Roese MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 233a7f480d9SStefan Roese MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 234a7f480d9SStefan Roese 235a7f480d9SStefan Roese /* ENET1 reset */ 236a7f480d9SStefan Roese MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), 237a7f480d9SStefan Roese /* ENET1 interrupt */ 238a7f480d9SStefan Roese MX6_PAD_CSI_PIXCLK__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), 239a7f480d9SStefan Roese }; 240a7f480d9SStefan Roese 241a7f480d9SStefan Roese #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17) 242a7f480d9SStefan Roese 243a7f480d9SStefan Roese int board_eth_init(bd_t *bis) 244a7f480d9SStefan Roese { 245a7f480d9SStefan Roese int ret; 246a7f480d9SStefan Roese 247a7f480d9SStefan Roese imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 248a7f480d9SStefan Roese 249a7f480d9SStefan Roese /* Reset LAN8742 PHY */ 250a7f480d9SStefan Roese ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset"); 251a7f480d9SStefan Roese if (!ret) 252a7f480d9SStefan Roese gpio_direction_output(ENET_PHY_RESET_GPIO , 0); 253a7f480d9SStefan Roese mdelay(10); 254a7f480d9SStefan Roese gpio_set_value(ENET_PHY_RESET_GPIO, 1); 255a7f480d9SStefan Roese mdelay(10); 256a7f480d9SStefan Roese 257a7f480d9SStefan Roese return cpu_eth_init(bis); 258a7f480d9SStefan Roese } 259a7f480d9SStefan Roese 260a7f480d9SStefan Roese static int setup_fec(int fec_id) 261a7f480d9SStefan Roese { 262a7f480d9SStefan Roese struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 263a7f480d9SStefan Roese int ret; 264a7f480d9SStefan Roese 265a7f480d9SStefan Roese /* 266a7f480d9SStefan Roese * Use 50M anatop loopback REF_CLK1 for ENET1, 267a7f480d9SStefan Roese * clear gpr1[13], set gpr1[17]. 268a7f480d9SStefan Roese */ 269a7f480d9SStefan Roese clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 270a7f480d9SStefan Roese IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); 271a7f480d9SStefan Roese 272a7f480d9SStefan Roese ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); 273a7f480d9SStefan Roese if (ret) 274a7f480d9SStefan Roese return ret; 275a7f480d9SStefan Roese 276a7f480d9SStefan Roese enable_enet_clk(1); 277a7f480d9SStefan Roese 278a7f480d9SStefan Roese return 0; 279a7f480d9SStefan Roese } 280a7f480d9SStefan Roese 281a7f480d9SStefan Roese int board_phy_config(struct phy_device *phydev) 282a7f480d9SStefan Roese { 283a7f480d9SStefan Roese if (phydev->drv->config) 284a7f480d9SStefan Roese phydev->drv->config(phydev); 285a7f480d9SStefan Roese 286a7f480d9SStefan Roese return 0; 287a7f480d9SStefan Roese } 288a7f480d9SStefan Roese 289a7f480d9SStefan Roese int board_early_init_f(void) 290a7f480d9SStefan Roese { 291a7f480d9SStefan Roese setup_iomux_uart(); 292a7f480d9SStefan Roese 293a7f480d9SStefan Roese return 0; 294a7f480d9SStefan Roese } 295a7f480d9SStefan Roese 296a7f480d9SStefan Roese int board_init(void) 297a7f480d9SStefan Roese { 298a7f480d9SStefan Roese /* Address of boot parameters */ 299a7f480d9SStefan Roese gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 300a7f480d9SStefan Roese 301a7f480d9SStefan Roese setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 302a7f480d9SStefan Roese setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 303a7f480d9SStefan Roese setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); 304a7f480d9SStefan Roese 305a7f480d9SStefan Roese setup_fec(CONFIG_FEC_ENET_DEV); 306a7f480d9SStefan Roese 307a7f480d9SStefan Roese setup_usb(); 308a7f480d9SStefan Roese 309a7f480d9SStefan Roese return 0; 310a7f480d9SStefan Roese } 311a7f480d9SStefan Roese 312a7f480d9SStefan Roese static const struct boot_mode board_boot_modes[] = { 313a7f480d9SStefan Roese /* 8 bit bus width */ 314a7f480d9SStefan Roese {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)}, 315a7f480d9SStefan Roese { NULL, 0 }, 316a7f480d9SStefan Roese }; 317a7f480d9SStefan Roese 318a7f480d9SStefan Roese int board_late_init(void) 319a7f480d9SStefan Roese { 320a7f480d9SStefan Roese add_board_boot_modes(board_boot_modes); 321*382bee57SSimon Glass env_set("board_name", "xpress"); 322a7f480d9SStefan Roese 323a7f480d9SStefan Roese return 0; 324a7f480d9SStefan Roese } 325a7f480d9SStefan Roese 326a7f480d9SStefan Roese int checkboard(void) 327a7f480d9SStefan Roese { 328a7f480d9SStefan Roese puts("Board: CCV-EVA xPress\n"); 329a7f480d9SStefan Roese 330a7f480d9SStefan Roese return 0; 331a7f480d9SStefan Roese } 332