1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SPL specific code for CCV xPress 4 * 5 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 6 */ 7 8 #include <common.h> 9 #include <spl.h> 10 #include <asm/io.h> 11 #include <asm/arch/mx6-ddr.h> 12 #include <asm/arch/crm_regs.h> 13 14 /* Configuration for IM IME1G16D3EEBG-15EI, 64M x 16 -> 128MiB */ 15 16 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 17 .grp_addds = 0x00000030, 18 .grp_ddrmode_ctl = 0x00020000, 19 .grp_b0ds = 0x00000030, 20 .grp_ctlds = 0x00000030, 21 .grp_b1ds = 0x00000030, 22 .grp_ddrpke = 0x00000000, 23 .grp_ddrmode = 0x00020000, 24 .grp_ddr_type = 0x000c0000, 25 }; 26 27 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 28 .dram_dqm0 = 0x00000030, 29 .dram_dqm1 = 0x00000030, 30 .dram_ras = 0x00000030, 31 .dram_cas = 0x00000030, 32 .dram_odt0 = 0x00000030, 33 .dram_odt1 = 0x00000030, 34 .dram_sdba2 = 0x00000000, 35 .dram_sdclk_0 = 0x00000008, 36 .dram_sdqs0 = 0x00000038, 37 .dram_sdqs1 = 0x00000030, 38 .dram_reset = 0x00000030, 39 }; 40 41 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 42 .p0_mpwldectrl0 = 0x00000000, 43 .p0_mpdgctrl0 = 0x4164015C, 44 .p0_mprddlctl = 0x40404446, 45 .p0_mpwrdlctl = 0x40405A52, 46 }; 47 48 struct mx6_ddr_sysinfo ddr_sysinfo = { 49 .dsize = 0, 50 .cs_density = 20, 51 .ncs = 1, 52 .cs1_mirror = 0, 53 .rtt_wr = 2, 54 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 55 .walat = 1, /* Write additional latency */ 56 .ralat = 5, /* Read additional latency */ 57 .mif3_mode = 3, /* Command prediction working mode */ 58 .bi_on = 1, /* Bank interleaving enabled */ 59 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 60 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 61 .ddr_type = DDR_TYPE_DDR3, 62 .refsel = 1, /* Refresh cycles at 32KHz */ 63 .refr = 7, /* 8 refresh commands per refresh cycle */ 64 }; 65 66 static struct mx6_ddr3_cfg mem_ddr = { 67 .mem_speed = 800, 68 .density = 4, 69 .width = 16, 70 .banks = 8, 71 .rowaddr = 13, 72 .coladdr = 10, 73 .pagesz = 2, 74 .trcd = 1375, 75 .trcmin = 4875, 76 .trasmin = 3500, 77 }; 78 79 static void ccgr_init(void) 80 { 81 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 82 83 writel(0xFFFFFFFF, &ccm->CCGR0); 84 writel(0xFFFFFFFF, &ccm->CCGR1); 85 writel(0xFFFFFFFF, &ccm->CCGR2); 86 writel(0xFFFFFFFF, &ccm->CCGR3); 87 writel(0xFFFFFFFF, &ccm->CCGR4); 88 writel(0xFFFFFFFF, &ccm->CCGR5); 89 writel(0xFFFFFFFF, &ccm->CCGR6); 90 writel(0xFFFFFFFF, &ccm->CCGR7); 91 } 92 93 static void spl_dram_init(void) 94 { 95 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 96 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 97 } 98 99 void board_init_f(ulong dummy) 100 { 101 /* Setup AIPS and disable watchdog */ 102 arch_cpu_init(); 103 104 ccgr_init(); 105 106 /* Setup iomux and i2c */ 107 board_early_init_f(); 108 109 /* Setup GP timer */ 110 timer_init(); 111 112 /* UART clocks enabled and gd valid - init serial console */ 113 preloader_console_init(); 114 115 /* DDR initialization */ 116 spl_dram_init(); 117 } 118