1/* 2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Refer docs/README.imxmage for more details about how-to configure 7 * and create imximage boot image 8 * 9 * The syntax is taken as close as possible with the kwbimage 10 */ 11 12/* image version */ 13 14IMAGE_VERSION 2 15 16/* 17 * Boot Device : one of 18 * sd, nand 19 */ 20BOOT_FROM sd 21 22/* 23 * Device Configuration Data (DCD) 24 * 25 * Each entry must have the format: 26 * Addr-type Address Value 27 * 28 * where: 29 * Addr-type register length (1,2 or 4 bytes) 30 * Address absolute address of the register 31 * value value to be stored in the register 32 */ 33 34#define __ASSEMBLY__ 35#include <config.h> 36 37/* Enable all clocks */ 38DATA 4 0x020c4068 0xffffffff 39DATA 4 0x020c406c 0xffffffff 40DATA 4 0x020c4070 0xffffffff 41DATA 4 0x020c4074 0xffffffff 42DATA 4 0x020c4078 0xffffffff 43DATA 4 0x020c407c 0xffffffff 44DATA 4 0x020c4080 0xffffffff 45DATA 4 0x020c4084 0xffffffff 46 47/* ddr io type */ 48DATA 4 0x020e04b4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ 49DATA 4 0x020e04ac 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ 50 51/* clock */ 52DATA 4 0x020e027c 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */ 53 54/* control and address */ 55DATA 4 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ 56DATA 4 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ 57DATA 4 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ 58DATA 4 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ 59DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be 60 configured using Group Control Register: 61 IOMUXC_SW_PAD_CTL_GRP_CTLDS */ 62DATA 4 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */ 63DATA 4 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */ 64DATA 4 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ 65 66/* data strobes */ 67DATA 4 0x020e0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ 68DATA 4 0x020e0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */ 69DATA 4 0x020e0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */ 70 71/* data */ 72DATA 4 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ 73DATA 4 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ 74DATA 4 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ 75DATA 4 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ 76DATA 4 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ 77 78/* 79 * DDR Controller Registers 80 * 81 * Manufacturer: IM 82 * Device Part Number: IME1G16D3EEBG-15EI 83 * Clock Freq.: 400MHz 84 * Density per CS in Gb: 1 85 * Chip Selects used: 1 86 * Number of Banks: 8 87 * Row address: 13 88 * Column address: 10 89 * Data bus width 16 90 */ 91DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit 92 during MMDC set up */ 93 94/* 95 * Calibration setup 96 */ 97DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & 98 periodic HW ZQ calibration. */ 99 100/* 101 * For target board, may need to run write leveling calibration to fine tune 102 * these settings. 103 */ 104DATA 4 0x021b080c 0x00000000 105 106/* Read DQS Gating calibration */ 107DATA 4 0x021b083c 0x4164015C /* MPDGCTRL0 PHY0 */ 108 109/* Read calibration */ 110DATA 4 0x021b0848 0x40404446 /* MPRDDLCTL PHY0 */ 111 112/* Write calibration */ 113DATA 4 0x021b0850 0x40405A52 /* MPWRDLCTL PHY0 */ 114 115/* 116 * read data bit delay: (3 is the reccommended default value, although out of 117 * reset value is 0) 118 */ 119DATA 4 0x021b081c 0x33333333 /* DDR_PHY_P0_MPREDQBY0DL3 */ 120DATA 4 0x021b0820 0x33333333 /* DDR_PHY_P0_MPREDQBY1DL3 */ 121DATA 4 0x021b082c 0xF3333333 122DATA 4 0x021b0830 0xF3333333 123 124DATA 4 0x021b08c0 0x00921012 125 126/* Clock Fine Tuning */ 127DATA 4 0x021B0858 0x00000F00 /* [MMDC_MPSDCTRL] MMDC PHY CK Control Register */ 128 129/* Complete calibration by forced measurement: */ 130DATA 4 0x021b08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */ 131/* 132 * Calibration setup end 133 */ 134 135/* MMDC init: */ 136DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */ 137DATA 4 0x021b0008 0x1B333030 /* MMDC0_MDOTC */ 138DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */ 139DATA 4 0x021b0010 0xB66D0B63 /* MMDC0_MDCFG1 */ 140DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */ 141 142/* 143 * MDMISC: RALAT kept to the high level of 5. 144 * MDMISC: consider reducing RALAT if your 528MHz board design allow that. 145 * Lower RALAT benefits: 146 * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT 147 * to 3 148 * b. Small performence improvment 149 */ 150DATA 4 0x021b0018 0x00201740 /* MMDC0_MDMISC */ 151 152DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit 153 during MMDC set up */ 154 155DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */ 156DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */ 157DATA 4 0x021b0040 0x00000047 /* Chan0 CS0_END */ 158DATA 4 0x021b0000 0x82180000 /* MMDC0_MDCTL */ 159 160/* Mode register writes */ 161DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */ 162DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */ 163DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */ 164DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */ 165DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to 166 device on CS0 */ 167 168DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ 169DATA 4 0x021b0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */ 170DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */ 171DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will 172 enter automatically to self-refresh while the 173 number of idle cycle reached. */ 174DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially 175 the configuration bit as initialization is 176 complete) */ 177