1 /**
2  * (C) Copyright 2014, Cavium Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5 **/
6 
7 #include <common.h>
8 #include <malloc.h>
9 #include <errno.h>
10 #include <linux/compiler.h>
11 
12 #include <cavium/atf.h>
13 #include <asm/armv8/mmu.h>
14 
15 #if !CONFIG_IS_ENABLED(OF_CONTROL)
16 #include <dm/platdata.h>
17 #include <dm/platform_data/serial_pl01x.h>
18 
19 static const struct pl01x_serial_platdata serial0 = {
20 	.base = CONFIG_SYS_SERIAL0,
21 	.type = TYPE_PL011,
22 	.clock = 0,
23 	.skip_init = true,
24 };
25 
26 U_BOOT_DEVICE(thunderx_serial0) = {
27 	.name = "serial_pl01x",
28 	.platdata = &serial0,
29 };
30 
31 static const struct pl01x_serial_platdata serial1 = {
32 	.base = CONFIG_SYS_SERIAL1,
33 	.type = TYPE_PL011,
34 	.clock = 0,
35 	.skip_init = true,
36 };
37 
38 U_BOOT_DEVICE(thunderx_serial1) = {
39 	.name = "serial_pl01x",
40 	.platdata = &serial1,
41 };
42 #endif
43 
44 DECLARE_GLOBAL_DATA_PTR;
45 
46 static struct mm_region thunderx_mem_map[] = {
47 	{
48 		.virt = 0x000000000000UL,
49 		.phys = 0x000000000000UL,
50 		.size = 0x40000000000UL,
51 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
52 	}, {
53 		.virt = 0x800000000000UL,
54 		.phys = 0x800000000000UL,
55 		.size = 0x40000000000UL,
56 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
57 			 PTE_BLOCK_NON_SHARE,
58 	}, {
59 		.virt = 0x840000000000UL,
60 		.phys = 0x840000000000UL,
61 		.size = 0x40000000000UL,
62 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
63 			 PTE_BLOCK_NON_SHARE,
64 	}, {
65 		/* List terminator */
66 		0,
67 	}
68 };
69 
70 struct mm_region *mem_map = thunderx_mem_map;
71 
72 int board_init(void)
73 {
74 	return 0;
75 }
76 
77 int timer_init(void)
78 {
79 	return 0;
80 }
81 
82 int dram_init(void)
83 {
84 	ssize_t node_count = atf_node_count();
85 	ssize_t dram_size;
86 	int node;
87 
88 	printf("Initializing\nNodes in system: %zd\n", node_count);
89 
90 	gd->ram_size = 0;
91 
92 	for (node = 0; node < node_count; node++) {
93 		dram_size = atf_dram_size(node);
94 		printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
95 		gd->ram_size += dram_size;
96 	}
97 
98 	gd->ram_size -= MEM_BASE;
99 
100 	*(unsigned long *)CPU_RELEASE_ADDR = 0;
101 
102 	puts("DRAM size:");
103 
104 	return 0;
105 }
106 
107 /*
108  * Board specific reset that is system reset.
109  */
110 void reset_cpu(ulong addr)
111 {
112 }
113 
114 /*
115  * Board specific ethernet initialization routine.
116  */
117 int board_eth_init(bd_t *bis)
118 {
119 	int rc = 0;
120 
121 	return rc;
122 }
123 
124 #ifdef CONFIG_PCI
125 void pci_init_board(void)
126 {
127 	printf("DEBUG: PCI Init TODO *****\n");
128 }
129 #endif
130