1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2746f985aSSergey Temerkhanov /**
3746f985aSSergey Temerkhanov  * (C) Copyright 2014, Cavium Inc.
4746f985aSSergey Temerkhanov **/
5746f985aSSergey Temerkhanov 
6746f985aSSergey Temerkhanov #include <common.h>
79d922450SSimon Glass #include <dm.h>
8746f985aSSergey Temerkhanov #include <malloc.h>
9746f985aSSergey Temerkhanov #include <errno.h>
10746f985aSSergey Temerkhanov #include <linux/compiler.h>
11746f985aSSergey Temerkhanov 
123ed2ece5SSergey Temerkhanov #include <cavium/atf.h>
13d473f0c6SAlexander Graf #include <asm/armv8/mmu.h>
143ed2ece5SSergey Temerkhanov 
15746f985aSSergey Temerkhanov #if !CONFIG_IS_ENABLED(OF_CONTROL)
16746f985aSSergey Temerkhanov #include <dm/platform_data/serial_pl01x.h>
17746f985aSSergey Temerkhanov 
18746f985aSSergey Temerkhanov static const struct pl01x_serial_platdata serial0 = {
19746f985aSSergey Temerkhanov 	.base = CONFIG_SYS_SERIAL0,
20746f985aSSergey Temerkhanov 	.type = TYPE_PL011,
21746f985aSSergey Temerkhanov 	.clock = 0,
22746f985aSSergey Temerkhanov 	.skip_init = true,
23746f985aSSergey Temerkhanov };
24746f985aSSergey Temerkhanov 
25746f985aSSergey Temerkhanov U_BOOT_DEVICE(thunderx_serial0) = {
26746f985aSSergey Temerkhanov 	.name = "serial_pl01x",
27746f985aSSergey Temerkhanov 	.platdata = &serial0,
28746f985aSSergey Temerkhanov };
29746f985aSSergey Temerkhanov 
30746f985aSSergey Temerkhanov static const struct pl01x_serial_platdata serial1 = {
31746f985aSSergey Temerkhanov 	.base = CONFIG_SYS_SERIAL1,
32746f985aSSergey Temerkhanov 	.type = TYPE_PL011,
33746f985aSSergey Temerkhanov 	.clock = 0,
34746f985aSSergey Temerkhanov 	.skip_init = true,
35746f985aSSergey Temerkhanov };
36746f985aSSergey Temerkhanov 
37746f985aSSergey Temerkhanov U_BOOT_DEVICE(thunderx_serial1) = {
38746f985aSSergey Temerkhanov 	.name = "serial_pl01x",
39746f985aSSergey Temerkhanov 	.platdata = &serial1,
40746f985aSSergey Temerkhanov };
41746f985aSSergey Temerkhanov #endif
42746f985aSSergey Temerkhanov 
43746f985aSSergey Temerkhanov DECLARE_GLOBAL_DATA_PTR;
44746f985aSSergey Temerkhanov 
45d473f0c6SAlexander Graf static struct mm_region thunderx_mem_map[] = {
46d473f0c6SAlexander Graf 	{
47cd4b0c5fSYork Sun 		.virt = 0x000000000000UL,
48cd4b0c5fSYork Sun 		.phys = 0x000000000000UL,
49d473f0c6SAlexander Graf 		.size = 0x40000000000UL,
50d473f0c6SAlexander Graf 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
51d473f0c6SAlexander Graf 	}, {
52cd4b0c5fSYork Sun 		.virt = 0x800000000000UL,
53cd4b0c5fSYork Sun 		.phys = 0x800000000000UL,
54d473f0c6SAlexander Graf 		.size = 0x40000000000UL,
55d473f0c6SAlexander Graf 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
56d473f0c6SAlexander Graf 			 PTE_BLOCK_NON_SHARE,
57d473f0c6SAlexander Graf 	}, {
58cd4b0c5fSYork Sun 		.virt = 0x840000000000UL,
59cd4b0c5fSYork Sun 		.phys = 0x840000000000UL,
60d473f0c6SAlexander Graf 		.size = 0x40000000000UL,
61d473f0c6SAlexander Graf 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
62d473f0c6SAlexander Graf 			 PTE_BLOCK_NON_SHARE,
63d473f0c6SAlexander Graf 	}, {
64d473f0c6SAlexander Graf 		/* List terminator */
65d473f0c6SAlexander Graf 		0,
66d473f0c6SAlexander Graf 	}
67d473f0c6SAlexander Graf };
68d473f0c6SAlexander Graf 
69d473f0c6SAlexander Graf struct mm_region *mem_map = thunderx_mem_map;
70d473f0c6SAlexander Graf 
board_init(void)71746f985aSSergey Temerkhanov int board_init(void)
72746f985aSSergey Temerkhanov {
73746f985aSSergey Temerkhanov 	return 0;
74746f985aSSergey Temerkhanov }
75746f985aSSergey Temerkhanov 
timer_init(void)76746f985aSSergey Temerkhanov int timer_init(void)
77746f985aSSergey Temerkhanov {
78746f985aSSergey Temerkhanov 	return 0;
79746f985aSSergey Temerkhanov }
80746f985aSSergey Temerkhanov 
dram_init(void)813ed2ece5SSergey Temerkhanov int dram_init(void)
823ed2ece5SSergey Temerkhanov {
833ed2ece5SSergey Temerkhanov 	ssize_t node_count = atf_node_count();
843ed2ece5SSergey Temerkhanov 	ssize_t dram_size;
853ed2ece5SSergey Temerkhanov 	int node;
863ed2ece5SSergey Temerkhanov 
873ed2ece5SSergey Temerkhanov 	printf("Initializing\nNodes in system: %zd\n", node_count);
883ed2ece5SSergey Temerkhanov 
893ed2ece5SSergey Temerkhanov 	gd->ram_size = 0;
903ed2ece5SSergey Temerkhanov 
913ed2ece5SSergey Temerkhanov 	for (node = 0; node < node_count; node++) {
923ed2ece5SSergey Temerkhanov 		dram_size = atf_dram_size(node);
933ed2ece5SSergey Temerkhanov 		printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
943ed2ece5SSergey Temerkhanov 		gd->ram_size += dram_size;
953ed2ece5SSergey Temerkhanov 	}
963ed2ece5SSergey Temerkhanov 
973ed2ece5SSergey Temerkhanov 	gd->ram_size -= MEM_BASE;
983ed2ece5SSergey Temerkhanov 
993ed2ece5SSergey Temerkhanov 	*(unsigned long *)CPU_RELEASE_ADDR = 0;
1003ed2ece5SSergey Temerkhanov 
1013ed2ece5SSergey Temerkhanov 	puts("DRAM size:");
1023ed2ece5SSergey Temerkhanov 
1033ed2ece5SSergey Temerkhanov 	return 0;
1043ed2ece5SSergey Temerkhanov }
1053ed2ece5SSergey Temerkhanov 
106746f985aSSergey Temerkhanov /*
107746f985aSSergey Temerkhanov  * Board specific reset that is system reset.
108746f985aSSergey Temerkhanov  */
reset_cpu(ulong addr)109746f985aSSergey Temerkhanov void reset_cpu(ulong addr)
110746f985aSSergey Temerkhanov {
111746f985aSSergey Temerkhanov }
112746f985aSSergey Temerkhanov 
113746f985aSSergey Temerkhanov /*
114746f985aSSergey Temerkhanov  * Board specific ethernet initialization routine.
115746f985aSSergey Temerkhanov  */
board_eth_init(bd_t * bis)116746f985aSSergey Temerkhanov int board_eth_init(bd_t *bis)
117746f985aSSergey Temerkhanov {
118746f985aSSergey Temerkhanov 	int rc = 0;
119746f985aSSergey Temerkhanov 
120746f985aSSergey Temerkhanov 	return rc;
121746f985aSSergey Temerkhanov }
122746f985aSSergey Temerkhanov 
123746f985aSSergey Temerkhanov #ifdef CONFIG_PCI
pci_init_board(void)124746f985aSSergey Temerkhanov void pci_init_board(void)
125746f985aSSergey Temerkhanov {
126746f985aSSergey Temerkhanov 	printf("DEBUG: PCI Init TODO *****\n");
127746f985aSSergey Temerkhanov }
128746f985aSSergey Temerkhanov #endif
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