1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2007-2013 4 * Stelian Pop <stelian.pop@leadtechdesign.com> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com> 7 * Mateusz Kulikowski <mateusz.kulikowski@gmail.com> 8 */ 9 10 #include <common.h> 11 #include <asm/arch/at91sam9_smc.h> 12 #include <asm/arch/at91_common.h> 13 #include <asm/arch/at91_matrix.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/gpio.h> 16 #include <asm-generic/gpio.h> 17 #include <asm/io.h> 18 #include <net.h> 19 #include <netdev.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 #ifdef CONFIG_CMD_NAND 24 static void usb_a9263_nand_hw_init(void) 25 { 26 unsigned long csa; 27 at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0; 28 at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX; 29 30 /* Enable CS3 */ 31 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; 32 writel(csa, &matrix->csa[0]); 33 34 /* Configure SMC CS3 for NAND/SmartMedia */ 35 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 36 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 37 &smc->cs[3].setup); 38 39 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 40 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 41 &smc->cs[3].pulse); 42 43 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 44 &smc->cs[3].cycle); 45 46 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 47 AT91_SMC_MODE_EXNW_DISABLE | 48 AT91_SMC_MODE_DBW_8 | 49 AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); 50 51 at91_periph_clk_enable(ATMEL_ID_PIOA); 52 at91_periph_clk_enable(ATMEL_ID_PIOCDE); 53 54 /* Configure RDY/BSY */ 55 gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy"); 56 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); 57 58 /* Enable NandFlash */ 59 gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable"); 60 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 61 } 62 #endif 63 64 #ifdef CONFIG_MACB 65 static void usb_a9263_macb_hw_init(void) 66 { 67 at91_periph_clk_enable(ATMEL_ID_EMAC); 68 69 /* 70 * Disable pull-up on: 71 * RXDV (PC25) => PHY normal mode (not Test mode) 72 * ERX0 (PE25) => PHY ADDR0 73 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 74 * 75 * PHY has internal weak pull-up/pull-down 76 */ 77 gpio_request(GPIO_PIN_PC(25), "PHY mode"); 78 gpio_direction_input(GPIO_PIN_PC(25)); 79 80 gpio_request(GPIO_PIN_PE(25), "PHY ADDR0"); 81 gpio_direction_input(GPIO_PIN_PE(25)); 82 83 gpio_request(GPIO_PIN_PE(26), "PHY ADDR1"); 84 gpio_direction_input(GPIO_PIN_PE(26)); 85 86 at91_phy_reset(); 87 88 /* It will set proper pinmux for ports PC25, PE25-26 */ 89 at91_macb_hw_init(); 90 } 91 #endif 92 93 int board_init(void) 94 { 95 /* adress of boot parameters */ 96 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 97 98 #ifdef CONFIG_CMD_NAND 99 usb_a9263_nand_hw_init(); 100 #endif 101 #ifdef CONFIG_MACB 102 usb_a9263_macb_hw_init(); 103 #endif 104 #ifdef CONFIG_USB_OHCI_NEW 105 at91_uhp_hw_init(); 106 #endif 107 return 0; 108 } 109 110 int dram_init(void) 111 { 112 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 113 CONFIG_SYS_SDRAM_SIZE); 114 return 0; 115 } 116 117 int board_eth_init(bd_t *bis) 118 { 119 int rc = 0; 120 121 #ifdef CONFIG_MACB 122 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x0001); 123 #endif 124 return rc; 125 } 126