1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2007 - 2013 Tensilica Inc. 4 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <dm.h> 10 #include <dm/platform_data/net_ethoc.h> 11 #include <linux/ctype.h> 12 #include <linux/string.h> 13 #include <linux/stringify.h> 14 #include <asm/global_data.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 /* 19 * Check board idendity. 20 * (Print information about the board to stdout.) 21 */ 22 23 24 #if defined(CONFIG_XTFPGA_LX60) 25 const char *board = "XT_AV60"; 26 const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / "; 27 #elif defined(CONFIG_XTFPGA_LX110) 28 const char *board = "XT_AV110"; 29 const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / "; 30 #elif defined(CONFIG_XTFPGA_LX200) 31 const char *board = "XT_AV200"; 32 const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / "; 33 #elif defined(CONFIG_XTFPGA_ML605) 34 const char *board = "XT_ML605"; 35 const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / "; 36 #elif defined(CONFIG_XTFPGA_KC705) 37 const char *board = "XT_KC705"; 38 const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / "; 39 #else 40 const char *board = "<unknown>"; 41 const char *description = ""; 42 #endif 43 44 int checkboard(void) 45 { 46 printf("Board: %s: %sTensilica bitstream\n", board, description); 47 return 0; 48 } 49 50 int dram_init_banksize(void) 51 { 52 gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE); 53 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; 54 55 return 0; 56 } 57 58 int board_postclk_init(void) 59 { 60 /* 61 * Obtain CPU clock frequency from board and cache in global 62 * data structure (Hz). Return 0 on success (OK to continue), 63 * else non-zero (hang). 64 */ 65 66 #ifdef CONFIG_SYS_FPGAREG_FREQ 67 gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ); 68 #else 69 /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */ 70 gd->cpu_clk = 50000000UL; 71 #endif 72 return 0; 73 } 74 75 /* 76 * Miscellaneous late initializations. 77 * The environment has been set up, so we can set the Ethernet address. 78 */ 79 80 int misc_init_r(void) 81 { 82 #ifdef CONFIG_CMD_NET 83 /* 84 * Initialize ethernet environment variables and board info. 85 * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6. 86 */ 87 88 char *s = env_get("ethaddr"); 89 if (s == 0) { 90 unsigned int x; 91 char s[] = __stringify(CONFIG_ETHBASE); 92 x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW) 93 & FPGAREG_MAC_MASK; 94 sprintf(&s[15], "%02x", x); 95 env_set("ethaddr", s); 96 } 97 #endif /* CONFIG_CMD_NET */ 98 99 return 0; 100 } 101 102 U_BOOT_DEVICE(sysreset) = { 103 .name = "xtfpga_sysreset", 104 }; 105 106 static struct ethoc_eth_pdata ethoc_pdata = { 107 .eth_pdata = { 108 .iobase = CONFIG_SYS_ETHOC_BASE, 109 }, 110 .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR, 111 }; 112 113 U_BOOT_DEVICE(ethoc) = { 114 .name = "ethoc", 115 .platdata = ðoc_pdata, 116 }; 117