1 /* 2 * (C) Copyright 2007 - 2013 Tensilica Inc. 3 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <command.h> 10 #include <dm/platdata.h> 11 #include <dm/platform_data/net_ethoc.h> 12 #include <linux/ctype.h> 13 #include <linux/string.h> 14 #include <linux/stringify.h> 15 #include <asm/global_data.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 /* 20 * Check board idendity. 21 * (Print information about the board to stdout.) 22 */ 23 24 25 #if defined(CONFIG_XTFPGA_LX60) 26 const char *board = "XT_AV60"; 27 const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / "; 28 #elif defined(CONFIG_XTFPGA_LX110) 29 const char *board = "XT_AV110"; 30 const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / "; 31 #elif defined(CONFIG_XTFPGA_LX200) 32 const char *board = "XT_AV200"; 33 const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / "; 34 #elif defined(CONFIG_XTFPGA_ML605) 35 const char *board = "XT_ML605"; 36 const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / "; 37 #elif defined(CONFIG_XTFPGA_KC705) 38 const char *board = "XT_KC705"; 39 const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / "; 40 #else 41 const char *board = "<unknown>"; 42 const char *description = ""; 43 #endif 44 45 int checkboard(void) 46 { 47 printf("Board: %s: %sTensilica bitstream\n", board, description); 48 return 0; 49 } 50 51 void dram_init_banksize(void) 52 { 53 gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE); 54 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; 55 } 56 57 int board_postclk_init(void) 58 { 59 /* 60 * Obtain CPU clock frequency from board and cache in global 61 * data structure (Hz). Return 0 on success (OK to continue), 62 * else non-zero (hang). 63 */ 64 65 #ifdef CONFIG_SYS_FPGAREG_FREQ 66 gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ); 67 #else 68 /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */ 69 gd->cpu_clk = 50000000UL; 70 #endif 71 return 0; 72 } 73 74 /* 75 * Miscellaneous late initializations. 76 * The environment has been set up, so we can set the Ethernet address. 77 */ 78 79 int misc_init_r(void) 80 { 81 #ifdef CONFIG_CMD_NET 82 /* 83 * Initialize ethernet environment variables and board info. 84 * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6. 85 */ 86 87 char *s = getenv("ethaddr"); 88 if (s == 0) { 89 unsigned int x; 90 char s[] = __stringify(CONFIG_ETHBASE); 91 x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW) 92 & FPGAREG_MAC_MASK; 93 sprintf(&s[15], "%02x", x); 94 setenv("ethaddr", s); 95 } 96 #endif /* CONFIG_CMD_NET */ 97 98 return 0; 99 } 100 101 U_BOOT_DEVICE(sysreset) = { 102 .name = "xtfpga_sysreset", 103 }; 104 105 static struct ethoc_eth_pdata ethoc_pdata = { 106 .eth_pdata = { 107 .iobase = CONFIG_SYS_ETHOC_BASE, 108 }, 109 .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR, 110 }; 111 112 U_BOOT_DEVICE(ethoc) = { 113 .name = "ethoc", 114 .platdata = ðoc_pdata, 115 }; 116