1#
2# Copyright (c) 2012 Michael Walle
3# Michael Walle <michael@walle.cc>
4#
5# SPDX-License-Identifier:	GPL-2.0+
6#
7# Refer doc/README.kwbimage for more details about how-to configure
8# and create kirkwood boot image
9#
10
11# Boot Media configurations
12BOOT_FROM spi
13
14# SOC registers configuration using bootrom header extension
15# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
16
17# Configure RGMII-0/1 interface pad voltage to 1.8V
18DATA 0xFFD100E0 0x1B1B9B9B
19
20# L2 RAM Timing 0
21DATA 0xFFD20134 0xBBBBBBBB
22# not further specified in HW manual, timing taken from original vendor port
23
24# L2 RAM Timing 1
25DATA 0xFFD20138 0x00BBBBBB
26# not further specified in HW manual, timing taken from original vendor port
27
28# DDR Configuration register
29DATA 0xFFD01400 0x43000618
30# bit13-0:  0x618, 1560 DDR2 clks refresh rate
31# bit23-14: 0 required
32# bit24:    1, enable exit self refresh mode on DDR access
33# bit25:    1 required
34# bit29-26: 0 required
35# bit31-30: 0b01 required
36
37# DDR Controller Control Low
38DATA 0xFFD01404 0x39543010
39# bit3-0:   0 required
40# bit4:     1, T2 mode, addr/cmd are driven for two cycles
41# bit5:     0, clk is driven during self refresh, we don't care for APX
42# bit6:     0, use recommended falling edge of clk for addr/cmd
43# bit11-7:  0 required
44# bit12:    1 required
45# bit13:    1 required
46# bit14:    0, input buffer always powered up
47# bit17-15: 0 required
48# bit18:    1, cpu lock transaction enabled
49# bit19:    0 required
50# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
51# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
52# bit30-28: 3 required
53# bit31:    0, no additional STARTBURST delay
54
55# DDR Timing (Low)
56DATA 0xFFD01408 0x22125441
57# bit3-0:   0x1, 18 cycle tRAS (tRAS[3-0])
58# bit7-4:   4, 5 cycle tRCD
59# bit11-8:  4, 5 cyle tRP
60# bit15-12: 5, 6 cyle tWR
61# bit19-16: 2, 3 cyle tWTR
62# bit20:    1, 18 cycle tRAS (tRAS[4])
63# bit23-21: 0 required
64# bit27-24: 2, 3 cycle tRRD
65# bit31-28: 2, 3 cyle tRTP
66
67# DDR Timing (High)
68DATA 0xFFD0140C 0x00000832
69# bit6-0:   0x32, 50 cycle tRFC
70# bit8-7:   0, 1 cycle tR2R
71# bit10-9:  0, 1 cyle tR2W
72# bit12-11: 1, 2 cylce tW2W
73# bit31-13: 0 required
74
75# DDR Address Control
76DATA 0xFFD01410 0x0000000C
77# bit1-0:   0, Cs0width=x8
78# bit3-2:   3, Cs0size=1Gbit
79# bit5-4:   0, Cs1width=nonexistent
80# bit7-6:   0, Cs1size=nonexistent
81# bit9-8:   0, Cs2width=nonexistent
82# bit11-10: 0, Cs2size=nonexistent
83# bit13-12: 0, Cs3width=nonexistent
84# bit15-14: 0, Cs3size=nonexistent
85# bit16:    0, Cs0AddrSel
86# bit17:    0, Cs1AddrSel
87# bit18:    0, Cs2AddrSel
88# bit19:    0, Cs3AddrSel
89# bit31-20: 0 required
90
91# DDR Open Pages Control
92DATA 0xFFD01414 0x00000000
93# bit0:    0, OPEn=OpenPage enabled
94# bit31-1: 0 required
95
96# DDR Operation
97DATA 0xFFD01418 0x00000000
98# bit3-0:   0, Cmd=Normal SDRAM Mode
99# bit31-4:  0 required
100
101# DDR Mode
102DATA 0xFFD0141C 0x00000652
103# bit2-0:   2, Burst Length (2 required)
104# bit3:     0, Burst Type (0 required)
105# bit6-4:   5, CAS Latency (CL) 5
106# bit7:     0, (Test Mode) Normal operation
107# bit8:     0, (Reset DLL) Normal operation
108# bit11-9:  3, Write recovery for auto-precharge (3 required)
109# bit12:    0, Fast Active power down exit time (0 required)
110# bit31-13: 0 required
111
112# DDR Extended Mode
113DATA 0xFFD01420 0x00000006
114# bit0:     0, DRAM DLL enabled
115# bit1:     1, DRAM drive strength reduced
116# bit2:     1, ODT control Rtt[0] (Rtt=1, 75 ohm termination)
117# bit5-3:   0 required
118# bit6:     0, ODT control Rtt[1] (Rtt=1, 75 ohm termination)
119# bit9-7:   0 required
120# bit10:    0, differential DQS enabled
121# bit11:    0 required
122# bit12:    0, DRAM output buffer enabled
123# bit31-13: 0 required
124
125# DDR Controller Control High
126DATA 0xFFD01424 0x0000F17F
127# bit2-0:   0x7 required
128# bit3:     1, MBUS Burst Chop disabled
129# bit6-4:   0x7 required
130# bit7:     0 required (???)
131# bit8:     1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
132# bit9:     0, no half clock cycle addition to dataout
133# bit10:    0, 1/4 clock cycle skew enabled for addr/ctl signals
134# bit11:    0, 1/4 clock cycle skew disabled for write mesh
135# bit15-12: 0xf required
136# bit31-16: 0 required
137
138# DDR2 ODT Read Timing (default values)
139DATA 0xFFD01428 0x00085520
140# bit3-0:   0 required
141# bit7-4:   2, 2 cycles from read command to assertion of M_ODT signal
142# bit11-8:  5, 5 cycles from read command to de-assertion of M_ODT signal
143# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
144# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
145# bit31-20: 0 required
146
147# DDR2 ODT Write Timing (default values)
148DATA 0xFFD0147C 0x00008552
149# bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
150# bit7-4:   5, 5 cycles from write command to de-assertion of M_ODT signal
151# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
152# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
153# bit31-16: 0 required
154
155# CS[0]n Base address
156DATA 0xFFD01500 0x00000000
157# at 0x0
158
159# CS[0]n Size
160DATA 0xFFD01504 0x0FFFFFF1
161# bit0:     1, Window enabled
162# bit1:     0, Write Protect disabled
163# bit3-2:   0x0, CS0 hit selected
164# bit23-4:  0xfffff required
165# bit31-24: 0x0f, Size (i.e. 256MB)
166
167# CS[1]n Size
168DATA 0xFFD0150C 0x00000000
169# window disabled
170
171# CS[2]n Size
172DATA 0xFFD01514 0x00000000
173# window disabled
174
175# CS[3]n Size
176DATA 0xFFD0151C 0x00000000
177# window disabled
178
179# DDR ODT Control (Low)
180DATA 0xFFD01494 0x00010000
181# bit3-0:   0b0000, (read) M_ODT[0] is not asserted during read from DRAM
182# bit7-4:   0b0000, (read) M_ODT[1] is not asserted during read from DRAM
183# bit15-8:  0 required
184# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
185# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
186# bit31-24: 0 required
187
188# DDR ODT Control (High)
189DATA 0xFFD01498 0x00000000
190# bit1-0:   0, M_ODT[0] assertion is controlled by ODT Control Low register
191# bit3-2:   0, M_ODT[1] assertion is controlled by ODT Control Low register
192# bit31-4   0 required
193
194# CPU ODT Control
195DATA 0xFFD0149C 0x0000E80F
196# bit3-0:   0b1111, internal ODT is asserted during read from DRAM bank 0-3
197# bit7-4:   0b0000, internal ODT is not asserted during write to DRAM bank 0-3
198# bit9-8:   0, Internal ODT assertion is controlled by fiels
199# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
200# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
201# bit14:    1, M_STARTBURST_IN ODT enabled
202# bit15:    1, DDR IO ODT Unit: Drive ODT calibration values
203# bit20-16: 0, Pad N channel driving strength for ODT
204# bit25-21: 0, Pad P channel driving strength for ODT
205# bit31-26: 0 required
206
207# DDR Initialization Control
208DATA 0xFFD01480 0x00000001
209# bit0:     1, enable DDR init upon this register write
210# bit31-1:  0, required
211
212# End of Header extension
213DATA 0x0 0x0
214