1 /* 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/io.h> 26 #include <asm/arch/clock.h> 27 #include <asm/arch/imx-regs.h> 28 #include <asm/arch/iomux.h> 29 #include <asm/arch/sys_proto.h> 30 #include <malloc.h> 31 #include <asm/arch/mx6-pins.h> 32 #include <asm/errno.h> 33 #include <asm/gpio.h> 34 #include <asm/imx-common/iomux-v3.h> 35 #include <asm/imx-common/mxc_i2c.h> 36 #include <asm/imx-common/boot_mode.h> 37 #include <mmc.h> 38 #include <fsl_esdhc.h> 39 #include <micrel.h> 40 #include <miiphy.h> 41 #include <netdev.h> 42 #include <linux/fb.h> 43 #include <ipu_pixfmt.h> 44 #include <asm/arch/crm_regs.h> 45 #include <asm/arch/mxc_hdmi.h> 46 #include <i2c.h> 47 48 DECLARE_GLOBAL_DATA_PTR; 49 50 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 51 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 52 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 53 54 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 55 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 56 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 57 58 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 59 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 60 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 61 62 #define SPI_PAD_CTRL (PAD_CTL_HYS | \ 63 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 64 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 65 66 #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 67 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 68 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 69 70 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 71 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 72 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 73 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 74 75 #define WEAK_PULLUP (PAD_CTL_PKE | PAD_CTL_PUE | \ 76 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 77 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 78 PAD_CTL_SRE_SLOW) 79 80 #define WEAK_PULLDOWN (PAD_CTL_PKE | PAD_CTL_PUE | \ 81 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 82 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 83 PAD_CTL_SRE_SLOW) 84 85 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) 86 87 int dram_init(void) 88 { 89 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); 90 91 return 0; 92 } 93 94 iomux_v3_cfg_t const uart1_pads[] = { 95 MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), 96 MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), 97 }; 98 99 iomux_v3_cfg_t const uart2_pads[] = { 100 MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), 101 MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), 102 }; 103 104 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 105 106 /* I2C1, SGTL5000 */ 107 struct i2c_pads_info i2c_pad_info0 = { 108 .scl = { 109 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 110 .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, 111 .gp = IMX_GPIO_NR(3, 21) 112 }, 113 .sda = { 114 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 115 .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, 116 .gp = IMX_GPIO_NR(3, 28) 117 } 118 }; 119 120 /* I2C2 Camera, MIPI */ 121 struct i2c_pads_info i2c_pad_info1 = { 122 .scl = { 123 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, 124 .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, 125 .gp = IMX_GPIO_NR(4, 12) 126 }, 127 .sda = { 128 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, 129 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, 130 .gp = IMX_GPIO_NR(4, 13) 131 } 132 }; 133 134 /* I2C3, J15 - RGB connector */ 135 struct i2c_pads_info i2c_pad_info2 = { 136 .scl = { 137 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, 138 .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, 139 .gp = IMX_GPIO_NR(1, 5) 140 }, 141 .sda = { 142 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, 143 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, 144 .gp = IMX_GPIO_NR(7, 11) 145 } 146 }; 147 148 iomux_v3_cfg_t const usdhc3_pads[] = { 149 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 150 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 151 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 152 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 153 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 154 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 155 MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 156 }; 157 158 iomux_v3_cfg_t const usdhc4_pads[] = { 159 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 160 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 161 MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 162 MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 163 MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 164 MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 165 MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 166 }; 167 168 iomux_v3_cfg_t const enet_pads1[] = { 169 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 170 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 171 MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 172 MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 173 MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 174 MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 175 MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 176 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 177 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 178 /* pin 35 - 1 (PHY_AD2) on reset */ 179 MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), 180 /* pin 32 - 1 - (MODE0) all */ 181 MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), 182 /* pin 31 - 1 - (MODE1) all */ 183 MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), 184 /* pin 28 - 1 - (MODE2) all */ 185 MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), 186 /* pin 27 - 1 - (MODE3) all */ 187 MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), 188 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ 189 MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), 190 /* pin 42 PHY nRST */ 191 MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), 192 MX6_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL), 193 }; 194 195 iomux_v3_cfg_t const enet_pads2[] = { 196 MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 197 MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 198 MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 199 MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 200 MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 201 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 202 }; 203 204 /* wl1271 pads on nitrogen6x */ 205 iomux_v3_cfg_t const wl12xx_pads[] = { 206 (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK) 207 | MUX_PAD_CTRL(WEAK_PULLDOWN), 208 (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK) 209 | MUX_PAD_CTRL(OUTPUT_40OHM), 210 (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK) 211 | MUX_PAD_CTRL(OUTPUT_40OHM), 212 }; 213 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) 214 #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15) 215 #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16) 216 217 /* Button assignments for J14 */ 218 static iomux_v3_cfg_t const button_pads[] = { 219 /* Menu */ 220 MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 221 /* Back */ 222 MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 223 /* Labelled Search (mapped to Power under Android) */ 224 MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 225 /* Home */ 226 MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 227 /* Volume Down */ 228 MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 229 /* Volume Up */ 230 MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 231 }; 232 233 static void setup_iomux_enet(void) 234 { 235 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */ 236 gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */ 237 gpio_direction_output(IMX_GPIO_NR(6, 30), 1); 238 gpio_direction_output(IMX_GPIO_NR(6, 25), 1); 239 gpio_direction_output(IMX_GPIO_NR(6, 27), 1); 240 gpio_direction_output(IMX_GPIO_NR(6, 28), 1); 241 gpio_direction_output(IMX_GPIO_NR(6, 29), 1); 242 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); 243 gpio_direction_output(IMX_GPIO_NR(6, 24), 1); 244 245 /* Need delay 10ms according to KSZ9021 spec */ 246 udelay(1000 * 10); 247 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */ 248 gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */ 249 250 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); 251 } 252 253 iomux_v3_cfg_t const usb_pads[] = { 254 MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), 255 }; 256 257 static void setup_iomux_uart(void) 258 { 259 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 260 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 261 } 262 263 #ifdef CONFIG_USB_EHCI_MX6 264 int board_ehci_hcd_init(int port) 265 { 266 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); 267 268 /* Reset USB hub */ 269 gpio_direction_output(IMX_GPIO_NR(7, 12), 0); 270 mdelay(2); 271 gpio_set_value(IMX_GPIO_NR(7, 12), 1); 272 273 return 0; 274 } 275 #endif 276 277 #ifdef CONFIG_FSL_ESDHC 278 struct fsl_esdhc_cfg usdhc_cfg[2] = { 279 {USDHC3_BASE_ADDR}, 280 {USDHC4_BASE_ADDR}, 281 }; 282 283 int board_mmc_getcd(struct mmc *mmc) 284 { 285 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 286 int ret; 287 288 if (cfg->esdhc_base == USDHC3_BASE_ADDR) { 289 gpio_direction_input(IMX_GPIO_NR(7, 0)); 290 ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); 291 } else { 292 gpio_direction_input(IMX_GPIO_NR(2, 6)); 293 ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); 294 } 295 296 return ret; 297 } 298 299 int board_mmc_init(bd_t *bis) 300 { 301 s32 status = 0; 302 u32 index = 0; 303 304 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 305 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 306 307 usdhc_cfg[0].max_bus_width = 4; 308 usdhc_cfg[1].max_bus_width = 4; 309 310 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 311 switch (index) { 312 case 0: 313 imx_iomux_v3_setup_multiple_pads( 314 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 315 break; 316 case 1: 317 imx_iomux_v3_setup_multiple_pads( 318 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 319 break; 320 default: 321 printf("Warning: you configured more USDHC controllers" 322 "(%d) then supported by the board (%d)\n", 323 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 324 return status; 325 } 326 327 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 328 } 329 330 return status; 331 } 332 #endif 333 334 #ifdef CONFIG_MXC_SPI 335 iomux_v3_cfg_t const ecspi1_pads[] = { 336 /* SS1 */ 337 MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), 338 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 339 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 340 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 341 }; 342 343 void setup_spi(void) 344 { 345 gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); 346 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, 347 ARRAY_SIZE(ecspi1_pads)); 348 } 349 #endif 350 351 int board_phy_config(struct phy_device *phydev) 352 { 353 /* min rx data delay */ 354 ksz9021_phy_extended_write(phydev, 355 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); 356 /* min tx data delay */ 357 ksz9021_phy_extended_write(phydev, 358 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); 359 /* max rx/tx clock delay, min rx/tx control */ 360 ksz9021_phy_extended_write(phydev, 361 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); 362 if (phydev->drv->config) 363 phydev->drv->config(phydev); 364 365 return 0; 366 } 367 368 int board_eth_init(bd_t *bis) 369 { 370 uint32_t base = IMX_FEC_BASE; 371 struct mii_dev *bus = NULL; 372 struct phy_device *phydev = NULL; 373 int ret; 374 375 setup_iomux_enet(); 376 377 #ifdef CONFIG_FEC_MXC 378 bus = fec_get_miibus(base, -1); 379 if (!bus) 380 return 0; 381 /* scan phy 4,5,6,7 */ 382 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); 383 if (!phydev) { 384 free(bus); 385 return 0; 386 } 387 printf("using phy at %d\n", phydev->addr); 388 ret = fec_probe(bis, -1, base, bus, phydev); 389 if (ret) { 390 printf("FEC MXC: %s:failed\n", __func__); 391 free(phydev); 392 free(bus); 393 } 394 #endif 395 return 0; 396 } 397 398 static void setup_buttons(void) 399 { 400 imx_iomux_v3_setup_multiple_pads(button_pads, 401 ARRAY_SIZE(button_pads)); 402 } 403 404 #ifdef CONFIG_CMD_SATA 405 406 int setup_sata(void) 407 { 408 struct iomuxc_base_regs *const iomuxc_regs 409 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; 410 int ret = enable_sata_clock(); 411 if (ret) 412 return ret; 413 414 clrsetbits_le32(&iomuxc_regs->gpr[13], 415 IOMUXC_GPR13_SATA_MASK, 416 IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB 417 |IOMUXC_GPR13_SATA_PHY_7_SATA2M 418 |IOMUXC_GPR13_SATA_SPEED_3G 419 |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) 420 |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED 421 |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 422 |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB 423 |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V 424 |IOMUXC_GPR13_SATA_PHY_1_SLOW); 425 426 return 0; 427 } 428 #endif 429 430 #if defined(CONFIG_VIDEO_IPUV3) 431 432 static iomux_v3_cfg_t const backlight_pads[] = { 433 /* Backlight on RGB connector: J15 */ 434 MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), 435 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) 436 437 /* Backlight on LVDS connector: J6 */ 438 MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), 439 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) 440 }; 441 442 static iomux_v3_cfg_t const rgb_pads[] = { 443 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 444 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, 445 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, 446 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, 447 MX6_PAD_DI0_PIN4__GPIO_4_20, 448 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, 449 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, 450 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, 451 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, 452 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, 453 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, 454 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, 455 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, 456 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, 457 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, 458 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, 459 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, 460 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, 461 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, 462 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, 463 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, 464 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, 465 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, 466 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, 467 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, 468 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, 469 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, 470 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, 471 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, 472 }; 473 474 struct display_info_t { 475 int bus; 476 int addr; 477 int pixfmt; 478 int (*detect)(struct display_info_t const *dev); 479 void (*enable)(struct display_info_t const *dev); 480 struct fb_videomode mode; 481 }; 482 483 484 static int detect_hdmi(struct display_info_t const *dev) 485 { 486 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 487 return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; 488 } 489 490 static void enable_hdmi(struct display_info_t const *dev) 491 { 492 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 493 u8 reg; 494 printf("%s: setup HDMI monitor\n", __func__); 495 reg = readb(&hdmi->phy_conf0); 496 reg |= HDMI_PHY_CONF0_PDZ_MASK; 497 writeb(reg, &hdmi->phy_conf0); 498 499 udelay(3000); 500 reg |= HDMI_PHY_CONF0_ENTMDS_MASK; 501 writeb(reg, &hdmi->phy_conf0); 502 udelay(3000); 503 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; 504 writeb(reg, &hdmi->phy_conf0); 505 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); 506 } 507 508 static int detect_i2c(struct display_info_t const *dev) 509 { 510 return ((0 == i2c_set_bus_num(dev->bus)) 511 && 512 (0 == i2c_probe(dev->addr))); 513 } 514 515 static void enable_lvds(struct display_info_t const *dev) 516 { 517 struct iomuxc *iomux = (struct iomuxc *) 518 IOMUXC_BASE_ADDR; 519 u32 reg = readl(&iomux->gpr[2]); 520 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; 521 writel(reg, &iomux->gpr[2]); 522 gpio_direction_output(LVDS_BACKLIGHT_GP, 1); 523 } 524 525 static void enable_rgb(struct display_info_t const *dev) 526 { 527 imx_iomux_v3_setup_multiple_pads( 528 rgb_pads, 529 ARRAY_SIZE(rgb_pads)); 530 gpio_direction_output(RGB_BACKLIGHT_GP, 1); 531 } 532 533 static struct display_info_t const displays[] = {{ 534 .bus = -1, 535 .addr = 0, 536 .pixfmt = IPU_PIX_FMT_RGB24, 537 .detect = detect_hdmi, 538 .enable = enable_hdmi, 539 .mode = { 540 .name = "HDMI", 541 .refresh = 60, 542 .xres = 1024, 543 .yres = 768, 544 .pixclock = 15385, 545 .left_margin = 220, 546 .right_margin = 40, 547 .upper_margin = 21, 548 .lower_margin = 7, 549 .hsync_len = 60, 550 .vsync_len = 10, 551 .sync = FB_SYNC_EXT, 552 .vmode = FB_VMODE_NONINTERLACED 553 } }, { 554 .bus = 2, 555 .addr = 0x4, 556 .pixfmt = IPU_PIX_FMT_LVDS666, 557 .detect = detect_i2c, 558 .enable = enable_lvds, 559 .mode = { 560 .name = "Hannstar-XGA", 561 .refresh = 60, 562 .xres = 1024, 563 .yres = 768, 564 .pixclock = 15385, 565 .left_margin = 220, 566 .right_margin = 40, 567 .upper_margin = 21, 568 .lower_margin = 7, 569 .hsync_len = 60, 570 .vsync_len = 10, 571 .sync = FB_SYNC_EXT, 572 .vmode = FB_VMODE_NONINTERLACED 573 } }, { 574 .bus = 2, 575 .addr = 0x38, 576 .pixfmt = IPU_PIX_FMT_LVDS666, 577 .detect = detect_i2c, 578 .enable = enable_lvds, 579 .mode = { 580 .name = "wsvga-lvds", 581 .refresh = 60, 582 .xres = 1024, 583 .yres = 600, 584 .pixclock = 15385, 585 .left_margin = 220, 586 .right_margin = 40, 587 .upper_margin = 21, 588 .lower_margin = 7, 589 .hsync_len = 60, 590 .vsync_len = 10, 591 .sync = FB_SYNC_EXT, 592 .vmode = FB_VMODE_NONINTERLACED 593 } }, { 594 .bus = 2, 595 .addr = 0x48, 596 .pixfmt = IPU_PIX_FMT_RGB666, 597 .detect = detect_i2c, 598 .enable = enable_rgb, 599 .mode = { 600 .name = "wvga-rgb", 601 .refresh = 57, 602 .xres = 800, 603 .yres = 480, 604 .pixclock = 37037, 605 .left_margin = 40, 606 .right_margin = 60, 607 .upper_margin = 10, 608 .lower_margin = 10, 609 .hsync_len = 20, 610 .vsync_len = 10, 611 .sync = 0, 612 .vmode = FB_VMODE_NONINTERLACED 613 } } }; 614 615 int board_video_skip(void) 616 { 617 int i; 618 int ret; 619 char const *panel = getenv("panel"); 620 if (!panel) { 621 for (i = 0; i < ARRAY_SIZE(displays); i++) { 622 struct display_info_t const *dev = displays+i; 623 if (dev->detect(dev)) { 624 panel = dev->mode.name; 625 printf("auto-detected panel %s\n", panel); 626 break; 627 } 628 } 629 if (!panel) { 630 panel = displays[0].mode.name; 631 printf("No panel detected: default to %s\n", panel); 632 } 633 } else { 634 for (i = 0; i < ARRAY_SIZE(displays); i++) { 635 if (!strcmp(panel, displays[i].mode.name)) 636 break; 637 } 638 } 639 if (i < ARRAY_SIZE(displays)) { 640 ret = ipuv3_fb_init(&displays[i].mode, 0, 641 displays[i].pixfmt); 642 if (!ret) { 643 displays[i].enable(displays+i); 644 printf("Display: %s (%ux%u)\n", 645 displays[i].mode.name, 646 displays[i].mode.xres, 647 displays[i].mode.yres); 648 } else 649 printf("LCD %s cannot be configured: %d\n", 650 displays[i].mode.name, ret); 651 } else { 652 printf("unsupported panel %s\n", panel); 653 ret = -EINVAL; 654 } 655 return (0 != ret); 656 } 657 658 static void setup_display(void) 659 { 660 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 661 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; 662 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 663 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 664 665 int reg; 666 667 /* Turn on LDB0,IPU,IPU DI0 clocks */ 668 reg = __raw_readl(&mxc_ccm->CCGR3); 669 reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 670 |MXC_CCM_CCGR3_LDB_DI0_MASK; 671 writel(reg, &mxc_ccm->CCGR3); 672 673 /* Turn on HDMI PHY clock */ 674 reg = __raw_readl(&mxc_ccm->CCGR2); 675 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK 676 |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; 677 writel(reg, &mxc_ccm->CCGR2); 678 679 /* clear HDMI PHY reset */ 680 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); 681 682 /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ 683 writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); 684 writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set); 685 686 /* set LDB0, LDB1 clk select to 011/011 */ 687 reg = readl(&mxc_ccm->cs2cdr); 688 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 689 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 690 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 691 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 692 writel(reg, &mxc_ccm->cs2cdr); 693 694 reg = readl(&mxc_ccm->cscmr2); 695 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 696 writel(reg, &mxc_ccm->cscmr2); 697 698 reg = readl(&mxc_ccm->chsccdr); 699 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK 700 |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK 701 |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); 702 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 703 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) 704 |(CHSCCDR_PODF_DIVIDE_BY_3 705 <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) 706 |(CHSCCDR_IPU_PRE_CLK_540M_PFD 707 <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); 708 writel(reg, &mxc_ccm->chsccdr); 709 710 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 711 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 712 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 713 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 714 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 715 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 716 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 717 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 718 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 719 writel(reg, &iomux->gpr[2]); 720 721 reg = readl(&iomux->gpr[3]); 722 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) 723 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 724 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 725 writel(reg, &iomux->gpr[3]); 726 727 /* backlights off until needed */ 728 imx_iomux_v3_setup_multiple_pads(backlight_pads, 729 ARRAY_SIZE(backlight_pads)); 730 gpio_direction_input(LVDS_BACKLIGHT_GP); 731 gpio_direction_input(RGB_BACKLIGHT_GP); 732 } 733 #endif 734 735 int board_early_init_f(void) 736 { 737 setup_iomux_uart(); 738 739 /* Disable wl1271 For Nitrogen6w */ 740 gpio_direction_input(WL12XX_WL_IRQ_GP); 741 gpio_direction_output(WL12XX_WL_ENABLE_GP, 0); 742 gpio_direction_output(WL12XX_BT_ENABLE_GP, 0); 743 744 imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); 745 setup_buttons(); 746 747 #if defined(CONFIG_VIDEO_IPUV3) 748 setup_display(); 749 #endif 750 return 0; 751 } 752 753 /* 754 * Do not overwrite the console 755 * Use always serial for U-Boot console 756 */ 757 int overwrite_console(void) 758 { 759 return 1; 760 } 761 762 int board_init(void) 763 { 764 /* address of boot parameters */ 765 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 766 767 #ifdef CONFIG_MXC_SPI 768 setup_spi(); 769 #endif 770 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 771 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 772 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 773 774 #ifdef CONFIG_CMD_SATA 775 setup_sata(); 776 #endif 777 778 return 0; 779 } 780 781 int checkboard(void) 782 { 783 if (gpio_get_value(WL12XX_WL_IRQ_GP)) 784 puts("Board: Nitrogen6X\n"); 785 else 786 puts("Board: SABRE Lite\n"); 787 788 return 0; 789 } 790 791 struct button_key { 792 char const *name; 793 unsigned gpnum; 794 char ident; 795 }; 796 797 static struct button_key const buttons[] = { 798 {"back", IMX_GPIO_NR(2, 2), 'B'}, 799 {"home", IMX_GPIO_NR(2, 4), 'H'}, 800 {"menu", IMX_GPIO_NR(2, 1), 'M'}, 801 {"search", IMX_GPIO_NR(2, 3), 'S'}, 802 {"volup", IMX_GPIO_NR(7, 13), 'V'}, 803 {"voldown", IMX_GPIO_NR(4, 5), 'v'}, 804 }; 805 806 /* 807 * generate a null-terminated string containing the buttons pressed 808 * returns number of keys pressed 809 */ 810 static int read_keys(char *buf) 811 { 812 int i, numpressed = 0; 813 for (i = 0; i < ARRAY_SIZE(buttons); i++) { 814 if (!gpio_get_value(buttons[i].gpnum)) 815 buf[numpressed++] = buttons[i].ident; 816 } 817 buf[numpressed] = '\0'; 818 return numpressed; 819 } 820 821 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 822 { 823 char envvalue[ARRAY_SIZE(buttons)+1]; 824 int numpressed = read_keys(envvalue); 825 setenv("keybd", envvalue); 826 return numpressed == 0; 827 } 828 829 U_BOOT_CMD( 830 kbd, 1, 1, do_kbd, 831 "Tests for keypresses, sets 'keybd' environment variable", 832 "Returns 0 (true) to shell if key is pressed." 833 ); 834 835 #ifdef CONFIG_PREBOOT 836 static char const kbd_magic_prefix[] = "key_magic"; 837 static char const kbd_command_prefix[] = "key_cmd"; 838 839 static void preboot_keys(void) 840 { 841 int numpressed; 842 char keypress[ARRAY_SIZE(buttons)+1]; 843 numpressed = read_keys(keypress); 844 if (numpressed) { 845 char *kbd_magic_keys = getenv("magic_keys"); 846 char *suffix; 847 /* 848 * loop over all magic keys 849 */ 850 for (suffix = kbd_magic_keys; *suffix; ++suffix) { 851 char *keys; 852 char magic[sizeof(kbd_magic_prefix) + 1]; 853 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); 854 keys = getenv(magic); 855 if (keys) { 856 if (!strcmp(keys, keypress)) 857 break; 858 } 859 } 860 if (*suffix) { 861 char cmd_name[sizeof(kbd_command_prefix) + 1]; 862 char *cmd; 863 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); 864 cmd = getenv(cmd_name); 865 if (cmd) { 866 setenv("preboot", cmd); 867 return; 868 } 869 } 870 } 871 } 872 #endif 873 874 #ifdef CONFIG_CMD_BMODE 875 static const struct boot_mode board_boot_modes[] = { 876 /* 4 bit bus width */ 877 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 878 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 879 {NULL, 0}, 880 }; 881 #endif 882 883 int misc_init_r(void) 884 { 885 #ifdef CONFIG_PREBOOT 886 preboot_keys(); 887 #endif 888 889 #ifdef CONFIG_CMD_BMODE 890 add_board_boot_modes(board_boot_modes); 891 #endif 892 return 0; 893 } 894