1 /* 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/sys_proto.h> 14 #include <malloc.h> 15 #include <asm/arch/mx6-pins.h> 16 #include <asm/errno.h> 17 #include <asm/gpio.h> 18 #include <asm/imx-common/iomux-v3.h> 19 #include <asm/imx-common/mxc_i2c.h> 20 #include <asm/imx-common/sata.h> 21 #include <asm/imx-common/boot_mode.h> 22 #include <asm/imx-common/video.h> 23 #include <mmc.h> 24 #include <fsl_esdhc.h> 25 #include <micrel.h> 26 #include <miiphy.h> 27 #include <netdev.h> 28 #include <asm/arch/crm_regs.h> 29 #include <asm/arch/mxc_hdmi.h> 30 #include <i2c.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) 34 35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 37 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 41 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 42 43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 45 46 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 47 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 48 49 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 50 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 51 52 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 54 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 55 56 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ 57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 58 PAD_CTL_SRE_SLOW) 59 60 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ 61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 62 PAD_CTL_HYS | PAD_CTL_SRE_SLOW) 63 64 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) 65 66 int dram_init(void) 67 { 68 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); 69 70 return 0; 71 } 72 73 iomux_v3_cfg_t const uart1_pads[] = { 74 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 75 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 76 }; 77 78 iomux_v3_cfg_t const uart2_pads[] = { 79 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 80 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 81 }; 82 83 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 84 85 /* I2C1, SGTL5000 */ 86 struct i2c_pads_info i2c_pad_info0 = { 87 .scl = { 88 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 89 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, 90 .gp = IMX_GPIO_NR(3, 21) 91 }, 92 .sda = { 93 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 94 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, 95 .gp = IMX_GPIO_NR(3, 28) 96 } 97 }; 98 99 /* I2C2 Camera, MIPI */ 100 struct i2c_pads_info i2c_pad_info1 = { 101 .scl = { 102 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, 103 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, 104 .gp = IMX_GPIO_NR(4, 12) 105 }, 106 .sda = { 107 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, 108 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, 109 .gp = IMX_GPIO_NR(4, 13) 110 } 111 }; 112 113 /* I2C3, J15 - RGB connector */ 114 struct i2c_pads_info i2c_pad_info2 = { 115 .scl = { 116 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, 117 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, 118 .gp = IMX_GPIO_NR(1, 5) 119 }, 120 .sda = { 121 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, 122 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, 123 .gp = IMX_GPIO_NR(7, 11) 124 } 125 }; 126 127 iomux_v3_cfg_t const usdhc3_pads[] = { 128 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 129 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 130 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 135 }; 136 137 iomux_v3_cfg_t const usdhc4_pads[] = { 138 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 139 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 140 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 141 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 142 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 143 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 144 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 145 }; 146 147 iomux_v3_cfg_t const enet_pads1[] = { 148 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 149 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 150 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 151 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 152 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 153 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 154 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 155 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 156 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 157 /* pin 35 - 1 (PHY_AD2) on reset */ 158 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), 159 /* pin 32 - 1 - (MODE0) all */ 160 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 161 /* pin 31 - 1 - (MODE1) all */ 162 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 163 /* pin 28 - 1 - (MODE2) all */ 164 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 165 /* pin 27 - 1 - (MODE3) all */ 166 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 167 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ 168 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), 169 /* pin 42 PHY nRST */ 170 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), 171 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 172 }; 173 174 iomux_v3_cfg_t const enet_pads2[] = { 175 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 176 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 177 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 178 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 179 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 180 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 181 }; 182 183 static iomux_v3_cfg_t const misc_pads[] = { 184 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), 185 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP), 186 MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP), 187 /* OTG Power enable */ 188 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM), 189 }; 190 191 /* wl1271 pads on nitrogen6x */ 192 iomux_v3_cfg_t const wl12xx_pads[] = { 193 (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK) 194 | MUX_PAD_CTRL(WEAK_PULLDOWN), 195 (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK) 196 | MUX_PAD_CTRL(OUTPUT_40OHM), 197 (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK) 198 | MUX_PAD_CTRL(OUTPUT_40OHM), 199 }; 200 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) 201 #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15) 202 #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16) 203 204 /* Button assignments for J14 */ 205 static iomux_v3_cfg_t const button_pads[] = { 206 /* Menu */ 207 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 208 /* Back */ 209 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 210 /* Labelled Search (mapped to Power under Android) */ 211 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 212 /* Home */ 213 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 214 /* Volume Down */ 215 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 216 /* Volume Up */ 217 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 218 }; 219 220 static void setup_iomux_enet(void) 221 { 222 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */ 223 gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */ 224 gpio_direction_output(IMX_GPIO_NR(6, 30), 1); 225 gpio_direction_output(IMX_GPIO_NR(6, 25), 1); 226 gpio_direction_output(IMX_GPIO_NR(6, 27), 1); 227 gpio_direction_output(IMX_GPIO_NR(6, 28), 1); 228 gpio_direction_output(IMX_GPIO_NR(6, 29), 1); 229 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); 230 gpio_direction_output(IMX_GPIO_NR(6, 24), 1); 231 232 /* Need delay 10ms according to KSZ9021 spec */ 233 udelay(1000 * 10); 234 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */ 235 gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */ 236 237 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); 238 } 239 240 iomux_v3_cfg_t const usb_pads[] = { 241 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 242 }; 243 244 static void setup_iomux_uart(void) 245 { 246 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 247 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 248 } 249 250 #ifdef CONFIG_USB_EHCI_MX6 251 int board_ehci_hcd_init(int port) 252 { 253 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); 254 255 /* Reset USB hub */ 256 gpio_direction_output(IMX_GPIO_NR(7, 12), 0); 257 mdelay(2); 258 gpio_set_value(IMX_GPIO_NR(7, 12), 1); 259 260 return 0; 261 } 262 263 int board_ehci_power(int port, int on) 264 { 265 if (port) 266 return 0; 267 gpio_set_value(GP_USB_OTG_PWR, on); 268 return 0; 269 } 270 271 #endif 272 273 #ifdef CONFIG_FSL_ESDHC 274 struct fsl_esdhc_cfg usdhc_cfg[2] = { 275 {USDHC3_BASE_ADDR}, 276 {USDHC4_BASE_ADDR}, 277 }; 278 279 int board_mmc_getcd(struct mmc *mmc) 280 { 281 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 282 int ret; 283 284 if (cfg->esdhc_base == USDHC3_BASE_ADDR) { 285 gpio_direction_input(IMX_GPIO_NR(7, 0)); 286 ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); 287 } else { 288 gpio_direction_input(IMX_GPIO_NR(2, 6)); 289 ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); 290 } 291 292 return ret; 293 } 294 295 int board_mmc_init(bd_t *bis) 296 { 297 s32 status = 0; 298 u32 index = 0; 299 300 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 301 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 302 303 usdhc_cfg[0].max_bus_width = 4; 304 usdhc_cfg[1].max_bus_width = 4; 305 306 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 307 switch (index) { 308 case 0: 309 imx_iomux_v3_setup_multiple_pads( 310 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 311 break; 312 case 1: 313 imx_iomux_v3_setup_multiple_pads( 314 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 315 break; 316 default: 317 printf("Warning: you configured more USDHC controllers" 318 "(%d) then supported by the board (%d)\n", 319 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 320 return status; 321 } 322 323 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 324 } 325 326 return status; 327 } 328 #endif 329 330 #ifdef CONFIG_MXC_SPI 331 iomux_v3_cfg_t const ecspi1_pads[] = { 332 /* SS1 */ 333 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 334 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 335 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 336 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 337 }; 338 339 void setup_spi(void) 340 { 341 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, 342 ARRAY_SIZE(ecspi1_pads)); 343 } 344 #endif 345 346 int board_phy_config(struct phy_device *phydev) 347 { 348 /* min rx data delay */ 349 ksz9021_phy_extended_write(phydev, 350 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); 351 /* min tx data delay */ 352 ksz9021_phy_extended_write(phydev, 353 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); 354 /* max rx/tx clock delay, min rx/tx control */ 355 ksz9021_phy_extended_write(phydev, 356 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); 357 if (phydev->drv->config) 358 phydev->drv->config(phydev); 359 360 return 0; 361 } 362 363 int board_eth_init(bd_t *bis) 364 { 365 uint32_t base = IMX_FEC_BASE; 366 struct mii_dev *bus = NULL; 367 struct phy_device *phydev = NULL; 368 int ret; 369 370 setup_iomux_enet(); 371 372 #ifdef CONFIG_FEC_MXC 373 bus = fec_get_miibus(base, -1); 374 if (!bus) 375 return 0; 376 /* scan phy 4,5,6,7 */ 377 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); 378 if (!phydev) { 379 free(bus); 380 return 0; 381 } 382 printf("using phy at %d\n", phydev->addr); 383 ret = fec_probe(bis, -1, base, bus, phydev); 384 if (ret) { 385 printf("FEC MXC: %s:failed\n", __func__); 386 free(phydev); 387 free(bus); 388 } 389 #endif 390 391 #ifdef CONFIG_CI_UDC 392 /* For otg ethernet*/ 393 usb_eth_initialize(bis); 394 #endif 395 return 0; 396 } 397 398 static void setup_buttons(void) 399 { 400 imx_iomux_v3_setup_multiple_pads(button_pads, 401 ARRAY_SIZE(button_pads)); 402 } 403 404 #if defined(CONFIG_VIDEO_IPUV3) 405 406 static iomux_v3_cfg_t const backlight_pads[] = { 407 /* Backlight on RGB connector: J15 */ 408 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 409 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) 410 411 /* Backlight on LVDS connector: J6 */ 412 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), 413 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) 414 }; 415 416 static iomux_v3_cfg_t const rgb_pads[] = { 417 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 418 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, 419 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, 420 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, 421 MX6_PAD_DI0_PIN4__GPIO4_IO20, 422 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, 423 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, 424 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, 425 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, 426 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, 427 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, 428 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, 429 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, 430 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, 431 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, 432 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, 433 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, 434 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, 435 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, 436 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, 437 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, 438 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, 439 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, 440 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, 441 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, 442 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, 443 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, 444 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, 445 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, 446 }; 447 448 static void do_enable_hdmi(struct display_info_t const *dev) 449 { 450 imx_enable_hdmi_phy(); 451 } 452 453 static int detect_i2c(struct display_info_t const *dev) 454 { 455 return ((0 == i2c_set_bus_num(dev->bus)) 456 && 457 (0 == i2c_probe(dev->addr))); 458 } 459 460 static void enable_lvds(struct display_info_t const *dev) 461 { 462 struct iomuxc *iomux = (struct iomuxc *) 463 IOMUXC_BASE_ADDR; 464 u32 reg = readl(&iomux->gpr[2]); 465 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; 466 writel(reg, &iomux->gpr[2]); 467 gpio_direction_output(LVDS_BACKLIGHT_GP, 1); 468 } 469 470 static void enable_rgb(struct display_info_t const *dev) 471 { 472 imx_iomux_v3_setup_multiple_pads( 473 rgb_pads, 474 ARRAY_SIZE(rgb_pads)); 475 gpio_direction_output(RGB_BACKLIGHT_GP, 1); 476 } 477 478 struct display_info_t const displays[] = {{ 479 .bus = -1, 480 .addr = 0, 481 .pixfmt = IPU_PIX_FMT_RGB24, 482 .detect = detect_hdmi, 483 .enable = do_enable_hdmi, 484 .mode = { 485 .name = "HDMI", 486 .refresh = 60, 487 .xres = 1024, 488 .yres = 768, 489 .pixclock = 15385, 490 .left_margin = 220, 491 .right_margin = 40, 492 .upper_margin = 21, 493 .lower_margin = 7, 494 .hsync_len = 60, 495 .vsync_len = 10, 496 .sync = FB_SYNC_EXT, 497 .vmode = FB_VMODE_NONINTERLACED 498 } }, { 499 .bus = 2, 500 .addr = 0x4, 501 .pixfmt = IPU_PIX_FMT_LVDS666, 502 .detect = detect_i2c, 503 .enable = enable_lvds, 504 .mode = { 505 .name = "Hannstar-XGA", 506 .refresh = 60, 507 .xres = 1024, 508 .yres = 768, 509 .pixclock = 15385, 510 .left_margin = 220, 511 .right_margin = 40, 512 .upper_margin = 21, 513 .lower_margin = 7, 514 .hsync_len = 60, 515 .vsync_len = 10, 516 .sync = FB_SYNC_EXT, 517 .vmode = FB_VMODE_NONINTERLACED 518 } }, { 519 .bus = 2, 520 .addr = 0x38, 521 .pixfmt = IPU_PIX_FMT_LVDS666, 522 .detect = detect_i2c, 523 .enable = enable_lvds, 524 .mode = { 525 .name = "wsvga-lvds", 526 .refresh = 60, 527 .xres = 1024, 528 .yres = 600, 529 .pixclock = 15385, 530 .left_margin = 220, 531 .right_margin = 40, 532 .upper_margin = 21, 533 .lower_margin = 7, 534 .hsync_len = 60, 535 .vsync_len = 10, 536 .sync = FB_SYNC_EXT, 537 .vmode = FB_VMODE_NONINTERLACED 538 } }, { 539 .bus = 2, 540 .addr = 0x48, 541 .pixfmt = IPU_PIX_FMT_RGB666, 542 .detect = detect_i2c, 543 .enable = enable_rgb, 544 .mode = { 545 .name = "wvga-rgb", 546 .refresh = 57, 547 .xres = 800, 548 .yres = 480, 549 .pixclock = 37037, 550 .left_margin = 40, 551 .right_margin = 60, 552 .upper_margin = 10, 553 .lower_margin = 10, 554 .hsync_len = 20, 555 .vsync_len = 10, 556 .sync = 0, 557 .vmode = FB_VMODE_NONINTERLACED 558 } } }; 559 size_t display_count = ARRAY_SIZE(displays); 560 561 static void setup_display(void) 562 { 563 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 564 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 565 int reg; 566 567 enable_ipu_clock(); 568 imx_setup_hdmi(); 569 /* Turn on LDB0,IPU,IPU DI0 clocks */ 570 reg = __raw_readl(&mxc_ccm->CCGR3); 571 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; 572 writel(reg, &mxc_ccm->CCGR3); 573 574 /* set LDB0, LDB1 clk select to 011/011 */ 575 reg = readl(&mxc_ccm->cs2cdr); 576 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 577 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 578 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 579 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 580 writel(reg, &mxc_ccm->cs2cdr); 581 582 reg = readl(&mxc_ccm->cscmr2); 583 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 584 writel(reg, &mxc_ccm->cscmr2); 585 586 reg = readl(&mxc_ccm->chsccdr); 587 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 588 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 589 writel(reg, &mxc_ccm->chsccdr); 590 591 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 592 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 593 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 594 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 595 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 596 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 597 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 598 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 599 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 600 writel(reg, &iomux->gpr[2]); 601 602 reg = readl(&iomux->gpr[3]); 603 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK 604 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 605 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 606 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 607 writel(reg, &iomux->gpr[3]); 608 609 /* backlights off until needed */ 610 imx_iomux_v3_setup_multiple_pads(backlight_pads, 611 ARRAY_SIZE(backlight_pads)); 612 gpio_direction_input(LVDS_BACKLIGHT_GP); 613 gpio_direction_input(RGB_BACKLIGHT_GP); 614 } 615 #endif 616 617 int board_early_init_f(void) 618 { 619 setup_iomux_uart(); 620 621 /* Disable wl1271 For Nitrogen6w */ 622 gpio_direction_input(WL12XX_WL_IRQ_GP); 623 gpio_direction_output(WL12XX_WL_ENABLE_GP, 0); 624 gpio_direction_output(WL12XX_BT_ENABLE_GP, 0); 625 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ 626 627 imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); 628 setup_buttons(); 629 630 #if defined(CONFIG_VIDEO_IPUV3) 631 setup_display(); 632 #endif 633 return 0; 634 } 635 636 /* 637 * Do not overwrite the console 638 * Use always serial for U-Boot console 639 */ 640 int overwrite_console(void) 641 { 642 return 1; 643 } 644 645 int board_init(void) 646 { 647 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 648 649 clrsetbits_le32(&iomuxc_regs->gpr[1], 650 IOMUXC_GPR1_OTG_ID_MASK, 651 IOMUXC_GPR1_OTG_ID_GPIO1); 652 653 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); 654 655 /* address of boot parameters */ 656 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 657 658 #ifdef CONFIG_MXC_SPI 659 setup_spi(); 660 #endif 661 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 662 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 663 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 664 665 #ifdef CONFIG_CMD_SATA 666 setup_sata(); 667 #endif 668 669 return 0; 670 } 671 672 int checkboard(void) 673 { 674 if (gpio_get_value(WL12XX_WL_IRQ_GP)) 675 puts("Board: Nitrogen6X\n"); 676 else 677 puts("Board: SABRE Lite\n"); 678 679 return 0; 680 } 681 682 struct button_key { 683 char const *name; 684 unsigned gpnum; 685 char ident; 686 }; 687 688 static struct button_key const buttons[] = { 689 {"back", IMX_GPIO_NR(2, 2), 'B'}, 690 {"home", IMX_GPIO_NR(2, 4), 'H'}, 691 {"menu", IMX_GPIO_NR(2, 1), 'M'}, 692 {"search", IMX_GPIO_NR(2, 3), 'S'}, 693 {"volup", IMX_GPIO_NR(7, 13), 'V'}, 694 {"voldown", IMX_GPIO_NR(4, 5), 'v'}, 695 }; 696 697 /* 698 * generate a null-terminated string containing the buttons pressed 699 * returns number of keys pressed 700 */ 701 static int read_keys(char *buf) 702 { 703 int i, numpressed = 0; 704 for (i = 0; i < ARRAY_SIZE(buttons); i++) { 705 if (!gpio_get_value(buttons[i].gpnum)) 706 buf[numpressed++] = buttons[i].ident; 707 } 708 buf[numpressed] = '\0'; 709 return numpressed; 710 } 711 712 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 713 { 714 char envvalue[ARRAY_SIZE(buttons)+1]; 715 int numpressed = read_keys(envvalue); 716 setenv("keybd", envvalue); 717 return numpressed == 0; 718 } 719 720 U_BOOT_CMD( 721 kbd, 1, 1, do_kbd, 722 "Tests for keypresses, sets 'keybd' environment variable", 723 "Returns 0 (true) to shell if key is pressed." 724 ); 725 726 #ifdef CONFIG_PREBOOT 727 static char const kbd_magic_prefix[] = "key_magic"; 728 static char const kbd_command_prefix[] = "key_cmd"; 729 730 static void preboot_keys(void) 731 { 732 int numpressed; 733 char keypress[ARRAY_SIZE(buttons)+1]; 734 numpressed = read_keys(keypress); 735 if (numpressed) { 736 char *kbd_magic_keys = getenv("magic_keys"); 737 char *suffix; 738 /* 739 * loop over all magic keys 740 */ 741 for (suffix = kbd_magic_keys; *suffix; ++suffix) { 742 char *keys; 743 char magic[sizeof(kbd_magic_prefix) + 1]; 744 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); 745 keys = getenv(magic); 746 if (keys) { 747 if (!strcmp(keys, keypress)) 748 break; 749 } 750 } 751 if (*suffix) { 752 char cmd_name[sizeof(kbd_command_prefix) + 1]; 753 char *cmd; 754 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); 755 cmd = getenv(cmd_name); 756 if (cmd) { 757 setenv("preboot", cmd); 758 return; 759 } 760 } 761 } 762 } 763 #endif 764 765 #ifdef CONFIG_CMD_BMODE 766 static const struct boot_mode board_boot_modes[] = { 767 /* 4 bit bus width */ 768 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 769 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 770 {NULL, 0}, 771 }; 772 #endif 773 774 int misc_init_r(void) 775 { 776 #ifdef CONFIG_PREBOOT 777 preboot_keys(); 778 #endif 779 780 #ifdef CONFIG_CMD_BMODE 781 add_board_boot_modes(board_boot_modes); 782 #endif 783 return 0; 784 } 785