1 /* 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/sys_proto.h> 14 #include <malloc.h> 15 #include <asm/arch/mx6-pins.h> 16 #include <asm/errno.h> 17 #include <asm/gpio.h> 18 #include <asm/imx-common/iomux-v3.h> 19 #include <asm/imx-common/mxc_i2c.h> 20 #include <asm/imx-common/sata.h> 21 #include <asm/imx-common/boot_mode.h> 22 #include <mmc.h> 23 #include <fsl_esdhc.h> 24 #include <micrel.h> 25 #include <miiphy.h> 26 #include <netdev.h> 27 #include <linux/fb.h> 28 #include <ipu_pixfmt.h> 29 #include <asm/arch/crm_regs.h> 30 #include <asm/arch/mxc_hdmi.h> 31 #include <i2c.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) 35 36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 38 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 39 40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 42 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 43 44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 46 47 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 48 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 49 50 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 52 53 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 54 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 55 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 56 57 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ 58 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 59 PAD_CTL_SRE_SLOW) 60 61 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ 62 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 63 PAD_CTL_HYS | PAD_CTL_SRE_SLOW) 64 65 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) 66 67 int dram_init(void) 68 { 69 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); 70 71 return 0; 72 } 73 74 iomux_v3_cfg_t const uart1_pads[] = { 75 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 76 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 77 }; 78 79 iomux_v3_cfg_t const uart2_pads[] = { 80 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 81 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 82 }; 83 84 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 85 86 /* I2C1, SGTL5000 */ 87 struct i2c_pads_info i2c_pad_info0 = { 88 .scl = { 89 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 90 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, 91 .gp = IMX_GPIO_NR(3, 21) 92 }, 93 .sda = { 94 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 95 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, 96 .gp = IMX_GPIO_NR(3, 28) 97 } 98 }; 99 100 /* I2C2 Camera, MIPI */ 101 struct i2c_pads_info i2c_pad_info1 = { 102 .scl = { 103 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, 104 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, 105 .gp = IMX_GPIO_NR(4, 12) 106 }, 107 .sda = { 108 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, 109 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, 110 .gp = IMX_GPIO_NR(4, 13) 111 } 112 }; 113 114 /* I2C3, J15 - RGB connector */ 115 struct i2c_pads_info i2c_pad_info2 = { 116 .scl = { 117 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, 118 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, 119 .gp = IMX_GPIO_NR(1, 5) 120 }, 121 .sda = { 122 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, 123 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, 124 .gp = IMX_GPIO_NR(7, 11) 125 } 126 }; 127 128 iomux_v3_cfg_t const usdhc3_pads[] = { 129 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 130 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 135 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 136 }; 137 138 iomux_v3_cfg_t const usdhc4_pads[] = { 139 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 140 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 141 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 142 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 143 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 144 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 145 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 146 }; 147 148 iomux_v3_cfg_t const enet_pads1[] = { 149 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 150 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 151 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 152 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 153 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 154 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 155 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 156 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 157 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 158 /* pin 35 - 1 (PHY_AD2) on reset */ 159 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), 160 /* pin 32 - 1 - (MODE0) all */ 161 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 162 /* pin 31 - 1 - (MODE1) all */ 163 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 164 /* pin 28 - 1 - (MODE2) all */ 165 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 166 /* pin 27 - 1 - (MODE3) all */ 167 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 168 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ 169 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), 170 /* pin 42 PHY nRST */ 171 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), 172 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 173 }; 174 175 iomux_v3_cfg_t const enet_pads2[] = { 176 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 177 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 178 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 179 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 180 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 181 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 182 }; 183 184 static iomux_v3_cfg_t const misc_pads[] = { 185 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), 186 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP), 187 MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP), 188 /* OTG Power enable */ 189 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM), 190 }; 191 192 /* wl1271 pads on nitrogen6x */ 193 iomux_v3_cfg_t const wl12xx_pads[] = { 194 (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK) 195 | MUX_PAD_CTRL(WEAK_PULLDOWN), 196 (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK) 197 | MUX_PAD_CTRL(OUTPUT_40OHM), 198 (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK) 199 | MUX_PAD_CTRL(OUTPUT_40OHM), 200 }; 201 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) 202 #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15) 203 #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16) 204 205 /* Button assignments for J14 */ 206 static iomux_v3_cfg_t const button_pads[] = { 207 /* Menu */ 208 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 209 /* Back */ 210 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 211 /* Labelled Search (mapped to Power under Android) */ 212 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 213 /* Home */ 214 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 215 /* Volume Down */ 216 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 217 /* Volume Up */ 218 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 219 }; 220 221 static void setup_iomux_enet(void) 222 { 223 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */ 224 gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */ 225 gpio_direction_output(IMX_GPIO_NR(6, 30), 1); 226 gpio_direction_output(IMX_GPIO_NR(6, 25), 1); 227 gpio_direction_output(IMX_GPIO_NR(6, 27), 1); 228 gpio_direction_output(IMX_GPIO_NR(6, 28), 1); 229 gpio_direction_output(IMX_GPIO_NR(6, 29), 1); 230 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); 231 gpio_direction_output(IMX_GPIO_NR(6, 24), 1); 232 233 /* Need delay 10ms according to KSZ9021 spec */ 234 udelay(1000 * 10); 235 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */ 236 gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */ 237 238 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); 239 } 240 241 iomux_v3_cfg_t const usb_pads[] = { 242 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 243 }; 244 245 static void setup_iomux_uart(void) 246 { 247 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 248 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 249 } 250 251 #ifdef CONFIG_USB_EHCI_MX6 252 int board_ehci_hcd_init(int port) 253 { 254 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); 255 256 /* Reset USB hub */ 257 gpio_direction_output(IMX_GPIO_NR(7, 12), 0); 258 mdelay(2); 259 gpio_set_value(IMX_GPIO_NR(7, 12), 1); 260 261 return 0; 262 } 263 264 int board_ehci_power(int port, int on) 265 { 266 if (port) 267 return 0; 268 gpio_set_value(GP_USB_OTG_PWR, on); 269 return 0; 270 } 271 272 #endif 273 274 #ifdef CONFIG_FSL_ESDHC 275 struct fsl_esdhc_cfg usdhc_cfg[2] = { 276 {USDHC3_BASE_ADDR}, 277 {USDHC4_BASE_ADDR}, 278 }; 279 280 int board_mmc_getcd(struct mmc *mmc) 281 { 282 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 283 int ret; 284 285 if (cfg->esdhc_base == USDHC3_BASE_ADDR) { 286 gpio_direction_input(IMX_GPIO_NR(7, 0)); 287 ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); 288 } else { 289 gpio_direction_input(IMX_GPIO_NR(2, 6)); 290 ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); 291 } 292 293 return ret; 294 } 295 296 int board_mmc_init(bd_t *bis) 297 { 298 s32 status = 0; 299 u32 index = 0; 300 301 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 302 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 303 304 usdhc_cfg[0].max_bus_width = 4; 305 usdhc_cfg[1].max_bus_width = 4; 306 307 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 308 switch (index) { 309 case 0: 310 imx_iomux_v3_setup_multiple_pads( 311 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 312 break; 313 case 1: 314 imx_iomux_v3_setup_multiple_pads( 315 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 316 break; 317 default: 318 printf("Warning: you configured more USDHC controllers" 319 "(%d) then supported by the board (%d)\n", 320 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 321 return status; 322 } 323 324 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 325 } 326 327 return status; 328 } 329 #endif 330 331 #ifdef CONFIG_MXC_SPI 332 iomux_v3_cfg_t const ecspi1_pads[] = { 333 /* SS1 */ 334 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL), 335 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 336 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 337 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 338 }; 339 340 void setup_spi(void) 341 { 342 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, 343 ARRAY_SIZE(ecspi1_pads)); 344 } 345 #endif 346 347 int board_phy_config(struct phy_device *phydev) 348 { 349 /* min rx data delay */ 350 ksz9021_phy_extended_write(phydev, 351 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); 352 /* min tx data delay */ 353 ksz9021_phy_extended_write(phydev, 354 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); 355 /* max rx/tx clock delay, min rx/tx control */ 356 ksz9021_phy_extended_write(phydev, 357 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); 358 if (phydev->drv->config) 359 phydev->drv->config(phydev); 360 361 return 0; 362 } 363 364 int board_eth_init(bd_t *bis) 365 { 366 uint32_t base = IMX_FEC_BASE; 367 struct mii_dev *bus = NULL; 368 struct phy_device *phydev = NULL; 369 int ret; 370 371 setup_iomux_enet(); 372 373 #ifdef CONFIG_FEC_MXC 374 bus = fec_get_miibus(base, -1); 375 if (!bus) 376 return 0; 377 /* scan phy 4,5,6,7 */ 378 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); 379 if (!phydev) { 380 free(bus); 381 return 0; 382 } 383 printf("using phy at %d\n", phydev->addr); 384 ret = fec_probe(bis, -1, base, bus, phydev); 385 if (ret) { 386 printf("FEC MXC: %s:failed\n", __func__); 387 free(phydev); 388 free(bus); 389 } 390 #endif 391 392 #ifdef CONFIG_CI_UDC 393 /* For otg ethernet*/ 394 usb_eth_initialize(bis); 395 #endif 396 return 0; 397 } 398 399 static void setup_buttons(void) 400 { 401 imx_iomux_v3_setup_multiple_pads(button_pads, 402 ARRAY_SIZE(button_pads)); 403 } 404 405 #if defined(CONFIG_VIDEO_IPUV3) 406 407 static iomux_v3_cfg_t const backlight_pads[] = { 408 /* Backlight on RGB connector: J15 */ 409 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 410 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) 411 412 /* Backlight on LVDS connector: J6 */ 413 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), 414 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) 415 }; 416 417 static iomux_v3_cfg_t const rgb_pads[] = { 418 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 419 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, 420 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, 421 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, 422 MX6_PAD_DI0_PIN4__GPIO4_IO20, 423 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, 424 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, 425 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, 426 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, 427 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, 428 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, 429 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, 430 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, 431 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, 432 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, 433 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, 434 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, 435 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, 436 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, 437 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, 438 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, 439 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, 440 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, 441 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, 442 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, 443 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, 444 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, 445 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, 446 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, 447 }; 448 449 struct display_info_t { 450 int bus; 451 int addr; 452 int pixfmt; 453 int (*detect)(struct display_info_t const *dev); 454 void (*enable)(struct display_info_t const *dev); 455 struct fb_videomode mode; 456 }; 457 458 459 static int detect_hdmi(struct display_info_t const *dev) 460 { 461 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; 462 return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT; 463 } 464 465 static void do_enable_hdmi(struct display_info_t const *dev) 466 { 467 imx_enable_hdmi_phy(); 468 } 469 470 static int detect_i2c(struct display_info_t const *dev) 471 { 472 return ((0 == i2c_set_bus_num(dev->bus)) 473 && 474 (0 == i2c_probe(dev->addr))); 475 } 476 477 static void enable_lvds(struct display_info_t const *dev) 478 { 479 struct iomuxc *iomux = (struct iomuxc *) 480 IOMUXC_BASE_ADDR; 481 u32 reg = readl(&iomux->gpr[2]); 482 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; 483 writel(reg, &iomux->gpr[2]); 484 gpio_direction_output(LVDS_BACKLIGHT_GP, 1); 485 } 486 487 static void enable_rgb(struct display_info_t const *dev) 488 { 489 imx_iomux_v3_setup_multiple_pads( 490 rgb_pads, 491 ARRAY_SIZE(rgb_pads)); 492 gpio_direction_output(RGB_BACKLIGHT_GP, 1); 493 } 494 495 static struct display_info_t const displays[] = {{ 496 .bus = -1, 497 .addr = 0, 498 .pixfmt = IPU_PIX_FMT_RGB24, 499 .detect = detect_hdmi, 500 .enable = do_enable_hdmi, 501 .mode = { 502 .name = "HDMI", 503 .refresh = 60, 504 .xres = 1024, 505 .yres = 768, 506 .pixclock = 15385, 507 .left_margin = 220, 508 .right_margin = 40, 509 .upper_margin = 21, 510 .lower_margin = 7, 511 .hsync_len = 60, 512 .vsync_len = 10, 513 .sync = FB_SYNC_EXT, 514 .vmode = FB_VMODE_NONINTERLACED 515 } }, { 516 .bus = 2, 517 .addr = 0x4, 518 .pixfmt = IPU_PIX_FMT_LVDS666, 519 .detect = detect_i2c, 520 .enable = enable_lvds, 521 .mode = { 522 .name = "Hannstar-XGA", 523 .refresh = 60, 524 .xres = 1024, 525 .yres = 768, 526 .pixclock = 15385, 527 .left_margin = 220, 528 .right_margin = 40, 529 .upper_margin = 21, 530 .lower_margin = 7, 531 .hsync_len = 60, 532 .vsync_len = 10, 533 .sync = FB_SYNC_EXT, 534 .vmode = FB_VMODE_NONINTERLACED 535 } }, { 536 .bus = 2, 537 .addr = 0x38, 538 .pixfmt = IPU_PIX_FMT_LVDS666, 539 .detect = detect_i2c, 540 .enable = enable_lvds, 541 .mode = { 542 .name = "wsvga-lvds", 543 .refresh = 60, 544 .xres = 1024, 545 .yres = 600, 546 .pixclock = 15385, 547 .left_margin = 220, 548 .right_margin = 40, 549 .upper_margin = 21, 550 .lower_margin = 7, 551 .hsync_len = 60, 552 .vsync_len = 10, 553 .sync = FB_SYNC_EXT, 554 .vmode = FB_VMODE_NONINTERLACED 555 } }, { 556 .bus = 2, 557 .addr = 0x48, 558 .pixfmt = IPU_PIX_FMT_RGB666, 559 .detect = detect_i2c, 560 .enable = enable_rgb, 561 .mode = { 562 .name = "wvga-rgb", 563 .refresh = 57, 564 .xres = 800, 565 .yres = 480, 566 .pixclock = 37037, 567 .left_margin = 40, 568 .right_margin = 60, 569 .upper_margin = 10, 570 .lower_margin = 10, 571 .hsync_len = 20, 572 .vsync_len = 10, 573 .sync = 0, 574 .vmode = FB_VMODE_NONINTERLACED 575 } } }; 576 577 int board_video_skip(void) 578 { 579 int i; 580 int ret; 581 char const *panel = getenv("panel"); 582 if (!panel) { 583 for (i = 0; i < ARRAY_SIZE(displays); i++) { 584 struct display_info_t const *dev = displays+i; 585 if (dev->detect(dev)) { 586 panel = dev->mode.name; 587 printf("auto-detected panel %s\n", panel); 588 break; 589 } 590 } 591 if (!panel) { 592 panel = displays[0].mode.name; 593 printf("No panel detected: default to %s\n", panel); 594 i = 0; 595 } 596 } else { 597 for (i = 0; i < ARRAY_SIZE(displays); i++) { 598 if (!strcmp(panel, displays[i].mode.name)) 599 break; 600 } 601 } 602 if (i < ARRAY_SIZE(displays)) { 603 ret = ipuv3_fb_init(&displays[i].mode, 0, 604 displays[i].pixfmt); 605 if (!ret) { 606 displays[i].enable(displays+i); 607 printf("Display: %s (%ux%u)\n", 608 displays[i].mode.name, 609 displays[i].mode.xres, 610 displays[i].mode.yres); 611 } else { 612 printf("LCD %s cannot be configured: %d\n", 613 displays[i].mode.name, ret); 614 } 615 } else { 616 printf("unsupported panel %s\n", panel); 617 ret = -EINVAL; 618 } 619 return (0 != ret); 620 } 621 622 static void setup_display(void) 623 { 624 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 625 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 626 int reg; 627 628 enable_ipu_clock(); 629 imx_setup_hdmi(); 630 /* Turn on LDB0,IPU,IPU DI0 clocks */ 631 reg = __raw_readl(&mxc_ccm->CCGR3); 632 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; 633 writel(reg, &mxc_ccm->CCGR3); 634 635 /* set LDB0, LDB1 clk select to 011/011 */ 636 reg = readl(&mxc_ccm->cs2cdr); 637 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 638 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 639 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 640 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 641 writel(reg, &mxc_ccm->cs2cdr); 642 643 reg = readl(&mxc_ccm->cscmr2); 644 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 645 writel(reg, &mxc_ccm->cscmr2); 646 647 reg = readl(&mxc_ccm->chsccdr); 648 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 649 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 650 writel(reg, &mxc_ccm->chsccdr); 651 652 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 653 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 654 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 655 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 656 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 657 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 658 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 659 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 660 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 661 writel(reg, &iomux->gpr[2]); 662 663 reg = readl(&iomux->gpr[3]); 664 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK 665 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 666 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 667 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 668 writel(reg, &iomux->gpr[3]); 669 670 /* backlights off until needed */ 671 imx_iomux_v3_setup_multiple_pads(backlight_pads, 672 ARRAY_SIZE(backlight_pads)); 673 gpio_direction_input(LVDS_BACKLIGHT_GP); 674 gpio_direction_input(RGB_BACKLIGHT_GP); 675 } 676 #endif 677 678 int board_early_init_f(void) 679 { 680 setup_iomux_uart(); 681 682 /* Disable wl1271 For Nitrogen6w */ 683 gpio_direction_input(WL12XX_WL_IRQ_GP); 684 gpio_direction_output(WL12XX_WL_ENABLE_GP, 0); 685 gpio_direction_output(WL12XX_BT_ENABLE_GP, 0); 686 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ 687 688 imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); 689 setup_buttons(); 690 691 #if defined(CONFIG_VIDEO_IPUV3) 692 setup_display(); 693 #endif 694 return 0; 695 } 696 697 /* 698 * Do not overwrite the console 699 * Use always serial for U-Boot console 700 */ 701 int overwrite_console(void) 702 { 703 return 1; 704 } 705 706 int board_init(void) 707 { 708 struct iomuxc_base_regs *const iomuxc_regs 709 = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; 710 711 clrsetbits_le32(&iomuxc_regs->gpr[1], 712 IOMUXC_GPR1_OTG_ID_MASK, 713 IOMUXC_GPR1_OTG_ID_GPIO1); 714 715 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); 716 717 /* address of boot parameters */ 718 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 719 720 #ifdef CONFIG_MXC_SPI 721 setup_spi(); 722 #endif 723 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 724 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 725 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 726 727 #ifdef CONFIG_CMD_SATA 728 setup_sata(); 729 #endif 730 731 return 0; 732 } 733 734 int checkboard(void) 735 { 736 if (gpio_get_value(WL12XX_WL_IRQ_GP)) 737 puts("Board: Nitrogen6X\n"); 738 else 739 puts("Board: SABRE Lite\n"); 740 741 return 0; 742 } 743 744 struct button_key { 745 char const *name; 746 unsigned gpnum; 747 char ident; 748 }; 749 750 static struct button_key const buttons[] = { 751 {"back", IMX_GPIO_NR(2, 2), 'B'}, 752 {"home", IMX_GPIO_NR(2, 4), 'H'}, 753 {"menu", IMX_GPIO_NR(2, 1), 'M'}, 754 {"search", IMX_GPIO_NR(2, 3), 'S'}, 755 {"volup", IMX_GPIO_NR(7, 13), 'V'}, 756 {"voldown", IMX_GPIO_NR(4, 5), 'v'}, 757 }; 758 759 /* 760 * generate a null-terminated string containing the buttons pressed 761 * returns number of keys pressed 762 */ 763 static int read_keys(char *buf) 764 { 765 int i, numpressed = 0; 766 for (i = 0; i < ARRAY_SIZE(buttons); i++) { 767 if (!gpio_get_value(buttons[i].gpnum)) 768 buf[numpressed++] = buttons[i].ident; 769 } 770 buf[numpressed] = '\0'; 771 return numpressed; 772 } 773 774 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 775 { 776 char envvalue[ARRAY_SIZE(buttons)+1]; 777 int numpressed = read_keys(envvalue); 778 setenv("keybd", envvalue); 779 return numpressed == 0; 780 } 781 782 U_BOOT_CMD( 783 kbd, 1, 1, do_kbd, 784 "Tests for keypresses, sets 'keybd' environment variable", 785 "Returns 0 (true) to shell if key is pressed." 786 ); 787 788 #ifdef CONFIG_PREBOOT 789 static char const kbd_magic_prefix[] = "key_magic"; 790 static char const kbd_command_prefix[] = "key_cmd"; 791 792 static void preboot_keys(void) 793 { 794 int numpressed; 795 char keypress[ARRAY_SIZE(buttons)+1]; 796 numpressed = read_keys(keypress); 797 if (numpressed) { 798 char *kbd_magic_keys = getenv("magic_keys"); 799 char *suffix; 800 /* 801 * loop over all magic keys 802 */ 803 for (suffix = kbd_magic_keys; *suffix; ++suffix) { 804 char *keys; 805 char magic[sizeof(kbd_magic_prefix) + 1]; 806 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); 807 keys = getenv(magic); 808 if (keys) { 809 if (!strcmp(keys, keypress)) 810 break; 811 } 812 } 813 if (*suffix) { 814 char cmd_name[sizeof(kbd_command_prefix) + 1]; 815 char *cmd; 816 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); 817 cmd = getenv(cmd_name); 818 if (cmd) { 819 setenv("preboot", cmd); 820 return; 821 } 822 } 823 } 824 } 825 #endif 826 827 #ifdef CONFIG_CMD_BMODE 828 static const struct boot_mode board_boot_modes[] = { 829 /* 4 bit bus width */ 830 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 831 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 832 {NULL, 0}, 833 }; 834 #endif 835 836 int misc_init_r(void) 837 { 838 #ifdef CONFIG_PREBOOT 839 preboot_keys(); 840 #endif 841 842 #ifdef CONFIG_CMD_BMODE 843 add_board_boot_modes(board_boot_modes); 844 #endif 845 return 0; 846 } 847