1 /* 2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/sys_proto.h> 14 #include <malloc.h> 15 #include <asm/arch/mx6-pins.h> 16 #include <asm/errno.h> 17 #include <asm/gpio.h> 18 #include <asm/imx-common/iomux-v3.h> 19 #include <asm/imx-common/mxc_i2c.h> 20 #include <asm/imx-common/sata.h> 21 #include <asm/imx-common/spi.h> 22 #include <asm/imx-common/boot_mode.h> 23 #include <asm/imx-common/video.h> 24 #include <mmc.h> 25 #include <fsl_esdhc.h> 26 #include <micrel.h> 27 #include <miiphy.h> 28 #include <netdev.h> 29 #include <asm/arch/crm_regs.h> 30 #include <asm/arch/mxc_hdmi.h> 31 #include <i2c.h> 32 #include <input.h> 33 #include <netdev.h> 34 #include <usb/ehci-fsl.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) 38 39 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 41 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 42 43 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 44 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 45 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 46 47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 49 50 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 51 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 52 53 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 54 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 55 56 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 58 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 59 60 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ 61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 62 PAD_CTL_SRE_SLOW) 63 64 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \ 65 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 66 PAD_CTL_HYS | PAD_CTL_SRE_SLOW) 67 68 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) 69 70 int dram_init(void) 71 { 72 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); 73 74 return 0; 75 } 76 77 static iomux_v3_cfg_t const uart1_pads[] = { 78 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 79 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 80 }; 81 82 static iomux_v3_cfg_t const uart2_pads[] = { 83 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 84 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 85 }; 86 87 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 88 89 /* I2C1, SGTL5000 */ 90 static struct i2c_pads_info i2c_pad_info0 = { 91 .scl = { 92 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 93 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, 94 .gp = IMX_GPIO_NR(3, 21) 95 }, 96 .sda = { 97 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 98 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, 99 .gp = IMX_GPIO_NR(3, 28) 100 } 101 }; 102 103 /* I2C2 Camera, MIPI */ 104 static struct i2c_pads_info i2c_pad_info1 = { 105 .scl = { 106 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, 107 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, 108 .gp = IMX_GPIO_NR(4, 12) 109 }, 110 .sda = { 111 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, 112 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, 113 .gp = IMX_GPIO_NR(4, 13) 114 } 115 }; 116 117 /* I2C3, J15 - RGB connector */ 118 static struct i2c_pads_info i2c_pad_info2 = { 119 .scl = { 120 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, 121 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, 122 .gp = IMX_GPIO_NR(1, 5) 123 }, 124 .sda = { 125 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, 126 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, 127 .gp = IMX_GPIO_NR(7, 11) 128 } 129 }; 130 131 static iomux_v3_cfg_t const usdhc2_pads[] = { 132 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 135 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 136 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 137 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 138 }; 139 140 static iomux_v3_cfg_t const usdhc3_pads[] = { 141 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 142 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 143 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 144 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 145 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 146 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 147 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 148 }; 149 150 static iomux_v3_cfg_t const usdhc4_pads[] = { 151 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 152 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 153 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 154 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 155 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 156 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 157 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 158 }; 159 160 static iomux_v3_cfg_t const enet_pads1[] = { 161 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 162 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 163 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 164 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 165 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 166 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 167 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 168 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 169 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 170 /* pin 35 - 1 (PHY_AD2) on reset */ 171 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), 172 /* pin 32 - 1 - (MODE0) all */ 173 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), 174 /* pin 31 - 1 - (MODE1) all */ 175 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 176 /* pin 28 - 1 - (MODE2) all */ 177 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 178 /* pin 27 - 1 - (MODE3) all */ 179 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 180 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ 181 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), 182 /* pin 42 PHY nRST */ 183 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), 184 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), 185 }; 186 187 static iomux_v3_cfg_t const enet_pads2[] = { 188 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 189 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 190 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 191 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 192 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 193 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 194 }; 195 196 static iomux_v3_cfg_t const misc_pads[] = { 197 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), 198 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP), 199 MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP), 200 /* OTG Power enable */ 201 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM), 202 }; 203 204 /* wl1271 pads on nitrogen6x */ 205 static iomux_v3_cfg_t const wl12xx_pads[] = { 206 (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK) 207 | MUX_PAD_CTRL(WEAK_PULLDOWN), 208 (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK) 209 | MUX_PAD_CTRL(OUTPUT_40OHM), 210 (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK) 211 | MUX_PAD_CTRL(OUTPUT_40OHM), 212 }; 213 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) 214 #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15) 215 #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16) 216 217 /* Button assignments for J14 */ 218 static iomux_v3_cfg_t const button_pads[] = { 219 /* Menu */ 220 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 221 /* Back */ 222 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 223 /* Labelled Search (mapped to Power under Android) */ 224 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 225 /* Home */ 226 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 227 /* Volume Down */ 228 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 229 /* Volume Up */ 230 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 231 }; 232 233 static void setup_iomux_enet(void) 234 { 235 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */ 236 gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */ 237 gpio_direction_output(IMX_GPIO_NR(6, 30), 1); 238 gpio_direction_output(IMX_GPIO_NR(6, 25), 1); 239 gpio_direction_output(IMX_GPIO_NR(6, 27), 1); 240 gpio_direction_output(IMX_GPIO_NR(6, 28), 1); 241 gpio_direction_output(IMX_GPIO_NR(6, 29), 1); 242 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); 243 gpio_direction_output(IMX_GPIO_NR(6, 24), 1); 244 245 /* Need delay 10ms according to KSZ9021 spec */ 246 udelay(1000 * 10); 247 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */ 248 gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */ 249 250 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); 251 udelay(100); /* Wait 100 us before using mii interface */ 252 } 253 254 static iomux_v3_cfg_t const usb_pads[] = { 255 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 256 }; 257 258 static void setup_iomux_uart(void) 259 { 260 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 261 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 262 } 263 264 #ifdef CONFIG_USB_EHCI_MX6 265 int board_ehci_hcd_init(int port) 266 { 267 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); 268 269 /* Reset USB hub */ 270 gpio_direction_output(IMX_GPIO_NR(7, 12), 0); 271 mdelay(2); 272 gpio_set_value(IMX_GPIO_NR(7, 12), 1); 273 274 return 0; 275 } 276 277 int board_ehci_power(int port, int on) 278 { 279 if (port) 280 return 0; 281 gpio_set_value(GP_USB_OTG_PWR, on); 282 return 0; 283 } 284 285 #endif 286 287 #ifdef CONFIG_FSL_ESDHC 288 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 289 {USDHC3_BASE_ADDR}, 290 {USDHC4_BASE_ADDR}, 291 }; 292 293 int board_mmc_getcd(struct mmc *mmc) 294 { 295 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 296 int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) : 297 IMX_GPIO_NR(2, 6); 298 299 gpio_direction_input(gp_cd); 300 return !gpio_get_value(gp_cd); 301 } 302 303 int board_mmc_init(bd_t *bis) 304 { 305 int ret; 306 u32 index = 0; 307 308 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 309 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 310 311 usdhc_cfg[0].max_bus_width = 4; 312 usdhc_cfg[1].max_bus_width = 4; 313 314 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 315 switch (index) { 316 case 0: 317 imx_iomux_v3_setup_multiple_pads( 318 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 319 break; 320 case 1: 321 imx_iomux_v3_setup_multiple_pads( 322 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 323 break; 324 default: 325 printf("Warning: you configured more USDHC controllers" 326 "(%d) then supported by the board (%d)\n", 327 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 328 return -EINVAL; 329 } 330 331 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 332 if (ret) 333 return ret; 334 } 335 336 return 0; 337 } 338 #endif 339 340 #ifdef CONFIG_MXC_SPI 341 int board_spi_cs_gpio(unsigned bus, unsigned cs) 342 { 343 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1; 344 } 345 346 static iomux_v3_cfg_t const ecspi1_pads[] = { 347 /* SS1 */ 348 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 349 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 350 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 351 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 352 }; 353 354 static void setup_spi(void) 355 { 356 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, 357 ARRAY_SIZE(ecspi1_pads)); 358 } 359 #endif 360 361 int board_phy_config(struct phy_device *phydev) 362 { 363 /* min rx data delay */ 364 ksz9021_phy_extended_write(phydev, 365 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); 366 /* min tx data delay */ 367 ksz9021_phy_extended_write(phydev, 368 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); 369 /* max rx/tx clock delay, min rx/tx control */ 370 ksz9021_phy_extended_write(phydev, 371 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); 372 if (phydev->drv->config) 373 phydev->drv->config(phydev); 374 375 return 0; 376 } 377 378 int board_eth_init(bd_t *bis) 379 { 380 uint32_t base = IMX_FEC_BASE; 381 struct mii_dev *bus = NULL; 382 struct phy_device *phydev = NULL; 383 int ret; 384 385 setup_iomux_enet(); 386 387 #ifdef CONFIG_FEC_MXC 388 bus = fec_get_miibus(base, -1); 389 if (!bus) 390 return 0; 391 /* scan phy 4,5,6,7 */ 392 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); 393 if (!phydev) { 394 free(bus); 395 return 0; 396 } 397 printf("using phy at %d\n", phydev->addr); 398 ret = fec_probe(bis, -1, base, bus, phydev); 399 if (ret) { 400 printf("FEC MXC: %s:failed\n", __func__); 401 free(phydev); 402 free(bus); 403 } 404 #endif 405 406 #ifdef CONFIG_CI_UDC 407 /* For otg ethernet*/ 408 usb_eth_initialize(bis); 409 #endif 410 return 0; 411 } 412 413 static void setup_buttons(void) 414 { 415 imx_iomux_v3_setup_multiple_pads(button_pads, 416 ARRAY_SIZE(button_pads)); 417 } 418 419 #if defined(CONFIG_VIDEO_IPUV3) 420 421 static iomux_v3_cfg_t const backlight_pads[] = { 422 /* Backlight on RGB connector: J15 */ 423 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 424 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) 425 426 /* Backlight on LVDS connector: J6 */ 427 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), 428 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) 429 }; 430 431 static iomux_v3_cfg_t const rgb_pads[] = { 432 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 433 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, 434 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, 435 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, 436 MX6_PAD_DI0_PIN4__GPIO4_IO20, 437 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, 438 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, 439 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, 440 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, 441 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, 442 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, 443 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, 444 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, 445 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, 446 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, 447 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, 448 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, 449 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, 450 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, 451 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, 452 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, 453 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, 454 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, 455 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, 456 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, 457 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, 458 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, 459 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, 460 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, 461 }; 462 463 static void do_enable_hdmi(struct display_info_t const *dev) 464 { 465 imx_enable_hdmi_phy(); 466 } 467 468 static int detect_i2c(struct display_info_t const *dev) 469 { 470 return ((0 == i2c_set_bus_num(dev->bus)) 471 && 472 (0 == i2c_probe(dev->addr))); 473 } 474 475 static void enable_lvds(struct display_info_t const *dev) 476 { 477 struct iomuxc *iomux = (struct iomuxc *) 478 IOMUXC_BASE_ADDR; 479 u32 reg = readl(&iomux->gpr[2]); 480 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; 481 writel(reg, &iomux->gpr[2]); 482 gpio_direction_output(LVDS_BACKLIGHT_GP, 1); 483 } 484 485 static void enable_lvds_jeida(struct display_info_t const *dev) 486 { 487 struct iomuxc *iomux = (struct iomuxc *) 488 IOMUXC_BASE_ADDR; 489 u32 reg = readl(&iomux->gpr[2]); 490 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT 491 |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA; 492 writel(reg, &iomux->gpr[2]); 493 gpio_direction_output(LVDS_BACKLIGHT_GP, 1); 494 } 495 496 static void enable_rgb(struct display_info_t const *dev) 497 { 498 imx_iomux_v3_setup_multiple_pads( 499 rgb_pads, 500 ARRAY_SIZE(rgb_pads)); 501 gpio_direction_output(RGB_BACKLIGHT_GP, 1); 502 } 503 504 struct display_info_t const displays[] = {{ 505 .bus = 1, 506 .addr = 0x50, 507 .pixfmt = IPU_PIX_FMT_RGB24, 508 .detect = detect_i2c, 509 .enable = do_enable_hdmi, 510 .mode = { 511 .name = "HDMI", 512 .refresh = 60, 513 .xres = 1024, 514 .yres = 768, 515 .pixclock = 15385, 516 .left_margin = 220, 517 .right_margin = 40, 518 .upper_margin = 21, 519 .lower_margin = 7, 520 .hsync_len = 60, 521 .vsync_len = 10, 522 .sync = FB_SYNC_EXT, 523 .vmode = FB_VMODE_NONINTERLACED 524 } }, { 525 .bus = 0, 526 .addr = 0, 527 .pixfmt = IPU_PIX_FMT_RGB24, 528 .detect = NULL, 529 .enable = enable_lvds_jeida, 530 .mode = { 531 .name = "LDB-WXGA", 532 .refresh = 60, 533 .xres = 1280, 534 .yres = 800, 535 .pixclock = 14065, 536 .left_margin = 40, 537 .right_margin = 40, 538 .upper_margin = 3, 539 .lower_margin = 80, 540 .hsync_len = 10, 541 .vsync_len = 10, 542 .sync = FB_SYNC_EXT, 543 .vmode = FB_VMODE_NONINTERLACED 544 } }, { 545 .bus = 0, 546 .addr = 0, 547 .pixfmt = IPU_PIX_FMT_RGB24, 548 .detect = NULL, 549 .enable = enable_lvds, 550 .mode = { 551 .name = "LDB-WXGA-S", 552 .refresh = 60, 553 .xres = 1280, 554 .yres = 800, 555 .pixclock = 14065, 556 .left_margin = 40, 557 .right_margin = 40, 558 .upper_margin = 3, 559 .lower_margin = 80, 560 .hsync_len = 10, 561 .vsync_len = 10, 562 .sync = FB_SYNC_EXT, 563 .vmode = FB_VMODE_NONINTERLACED 564 } }, { 565 .bus = 2, 566 .addr = 0x4, 567 .pixfmt = IPU_PIX_FMT_LVDS666, 568 .detect = detect_i2c, 569 .enable = enable_lvds, 570 .mode = { 571 .name = "Hannstar-XGA", 572 .refresh = 60, 573 .xres = 1024, 574 .yres = 768, 575 .pixclock = 15385, 576 .left_margin = 220, 577 .right_margin = 40, 578 .upper_margin = 21, 579 .lower_margin = 7, 580 .hsync_len = 60, 581 .vsync_len = 10, 582 .sync = FB_SYNC_EXT, 583 .vmode = FB_VMODE_NONINTERLACED 584 } }, { 585 .bus = 0, 586 .addr = 0, 587 .pixfmt = IPU_PIX_FMT_LVDS666, 588 .detect = NULL, 589 .enable = enable_lvds, 590 .mode = { 591 .name = "LG-9.7", 592 .refresh = 60, 593 .xres = 1024, 594 .yres = 768, 595 .pixclock = 15385, /* ~65MHz */ 596 .left_margin = 480, 597 .right_margin = 260, 598 .upper_margin = 16, 599 .lower_margin = 6, 600 .hsync_len = 250, 601 .vsync_len = 10, 602 .sync = FB_SYNC_EXT, 603 .vmode = FB_VMODE_NONINTERLACED 604 } }, { 605 .bus = 2, 606 .addr = 0x38, 607 .pixfmt = IPU_PIX_FMT_LVDS666, 608 .detect = detect_i2c, 609 .enable = enable_lvds, 610 .mode = { 611 .name = "wsvga-lvds", 612 .refresh = 60, 613 .xres = 1024, 614 .yres = 600, 615 .pixclock = 15385, 616 .left_margin = 220, 617 .right_margin = 40, 618 .upper_margin = 21, 619 .lower_margin = 7, 620 .hsync_len = 60, 621 .vsync_len = 10, 622 .sync = FB_SYNC_EXT, 623 .vmode = FB_VMODE_NONINTERLACED 624 } }, { 625 .bus = 2, 626 .addr = 0x10, 627 .pixfmt = IPU_PIX_FMT_RGB666, 628 .detect = detect_i2c, 629 .enable = enable_rgb, 630 .mode = { 631 .name = "fusion7", 632 .refresh = 60, 633 .xres = 800, 634 .yres = 480, 635 .pixclock = 33898, 636 .left_margin = 96, 637 .right_margin = 24, 638 .upper_margin = 3, 639 .lower_margin = 10, 640 .hsync_len = 72, 641 .vsync_len = 7, 642 .sync = 0x40000002, 643 .vmode = FB_VMODE_NONINTERLACED 644 } }, { 645 .bus = 0, 646 .addr = 0, 647 .pixfmt = IPU_PIX_FMT_RGB666, 648 .detect = NULL, 649 .enable = enable_rgb, 650 .mode = { 651 .name = "svga", 652 .refresh = 60, 653 .xres = 800, 654 .yres = 600, 655 .pixclock = 15385, 656 .left_margin = 220, 657 .right_margin = 40, 658 .upper_margin = 21, 659 .lower_margin = 7, 660 .hsync_len = 60, 661 .vsync_len = 10, 662 .sync = 0, 663 .vmode = FB_VMODE_NONINTERLACED 664 } }, { 665 .bus = 2, 666 .addr = 0x41, 667 .pixfmt = IPU_PIX_FMT_LVDS666, 668 .detect = detect_i2c, 669 .enable = enable_lvds, 670 .mode = { 671 .name = "amp1024x600", 672 .refresh = 60, 673 .xres = 1024, 674 .yres = 600, 675 .pixclock = 15385, 676 .left_margin = 220, 677 .right_margin = 40, 678 .upper_margin = 21, 679 .lower_margin = 7, 680 .hsync_len = 60, 681 .vsync_len = 10, 682 .sync = FB_SYNC_EXT, 683 .vmode = FB_VMODE_NONINTERLACED 684 } }, { 685 .bus = 0, 686 .addr = 0, 687 .pixfmt = IPU_PIX_FMT_LVDS666, 688 .detect = 0, 689 .enable = enable_lvds, 690 .mode = { 691 .name = "wvga-lvds", 692 .refresh = 57, 693 .xres = 800, 694 .yres = 480, 695 .pixclock = 15385, 696 .left_margin = 220, 697 .right_margin = 40, 698 .upper_margin = 21, 699 .lower_margin = 7, 700 .hsync_len = 60, 701 .vsync_len = 10, 702 .sync = FB_SYNC_EXT, 703 .vmode = FB_VMODE_NONINTERLACED 704 } }, { 705 .bus = 2, 706 .addr = 0x48, 707 .pixfmt = IPU_PIX_FMT_RGB666, 708 .detect = detect_i2c, 709 .enable = enable_rgb, 710 .mode = { 711 .name = "wvga-rgb", 712 .refresh = 57, 713 .xres = 800, 714 .yres = 480, 715 .pixclock = 37037, 716 .left_margin = 40, 717 .right_margin = 60, 718 .upper_margin = 10, 719 .lower_margin = 10, 720 .hsync_len = 20, 721 .vsync_len = 10, 722 .sync = 0, 723 .vmode = FB_VMODE_NONINTERLACED 724 } }, { 725 .bus = 0, 726 .addr = 0, 727 .pixfmt = IPU_PIX_FMT_RGB24, 728 .detect = NULL, 729 .enable = enable_rgb, 730 .mode = { 731 .name = "qvga", 732 .refresh = 60, 733 .xres = 320, 734 .yres = 240, 735 .pixclock = 37037, 736 .left_margin = 38, 737 .right_margin = 37, 738 .upper_margin = 16, 739 .lower_margin = 15, 740 .hsync_len = 30, 741 .vsync_len = 3, 742 .sync = 0, 743 .vmode = FB_VMODE_NONINTERLACED 744 } } }; 745 size_t display_count = ARRAY_SIZE(displays); 746 747 int board_cfb_skip(void) 748 { 749 return NULL != getenv("novideo"); 750 } 751 752 static void setup_display(void) 753 { 754 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 755 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 756 int reg; 757 758 enable_ipu_clock(); 759 imx_setup_hdmi(); 760 /* Turn on LDB0,IPU,IPU DI0 clocks */ 761 reg = __raw_readl(&mxc_ccm->CCGR3); 762 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; 763 writel(reg, &mxc_ccm->CCGR3); 764 765 /* set LDB0, LDB1 clk select to 011/011 */ 766 reg = readl(&mxc_ccm->cs2cdr); 767 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 768 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 769 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 770 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 771 writel(reg, &mxc_ccm->cs2cdr); 772 773 reg = readl(&mxc_ccm->cscmr2); 774 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 775 writel(reg, &mxc_ccm->cscmr2); 776 777 reg = readl(&mxc_ccm->chsccdr); 778 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 779 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 780 writel(reg, &mxc_ccm->chsccdr); 781 782 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 783 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 784 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW 785 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG 786 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT 787 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 788 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT 789 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 790 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 791 writel(reg, &iomux->gpr[2]); 792 793 reg = readl(&iomux->gpr[3]); 794 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK 795 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) 796 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 797 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 798 writel(reg, &iomux->gpr[3]); 799 800 /* backlights off until needed */ 801 imx_iomux_v3_setup_multiple_pads(backlight_pads, 802 ARRAY_SIZE(backlight_pads)); 803 gpio_direction_input(LVDS_BACKLIGHT_GP); 804 gpio_direction_input(RGB_BACKLIGHT_GP); 805 } 806 #endif 807 808 static iomux_v3_cfg_t const init_pads[] = { 809 /* SGTL5000 sys_mclk */ 810 NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM), 811 812 /* J5 - Camera MCLK */ 813 NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM), 814 815 /* wl1271 pads on nitrogen6x */ 816 /* WL12XX_WL_IRQ_GP */ 817 NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN), 818 /* WL12XX_WL_ENABLE_GP */ 819 NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM), 820 /* WL12XX_BT_ENABLE_GP */ 821 NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM), 822 /* USB otg power */ 823 NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM), 824 NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM), 825 NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM), 826 NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM), 827 NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM), 828 }; 829 830 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) 831 832 static unsigned gpios_out_low[] = { 833 /* Disable wl1271 */ 834 IMX_GPIO_NR(6, 15), /* disable wireless */ 835 IMX_GPIO_NR(6, 16), /* disable bluetooth */ 836 IMX_GPIO_NR(3, 22), /* disable USB otg power */ 837 IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */ 838 IMX_GPIO_NR(1, 8), /* ov5642 reset */ 839 }; 840 841 static unsigned gpios_out_high[] = { 842 IMX_GPIO_NR(1, 6), /* ov5642 powerdown */ 843 IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */ 844 }; 845 846 static void set_gpios(unsigned *p, int cnt, int val) 847 { 848 int i; 849 850 for (i = 0; i < cnt; i++) 851 gpio_direction_output(*p++, val); 852 } 853 854 int board_early_init_f(void) 855 { 856 setup_iomux_uart(); 857 858 set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1); 859 set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0); 860 gpio_direction_input(WL12XX_WL_IRQ_GP); 861 862 imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); 863 imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads)); 864 setup_buttons(); 865 866 #if defined(CONFIG_VIDEO_IPUV3) 867 setup_display(); 868 #endif 869 return 0; 870 } 871 872 /* 873 * Do not overwrite the console 874 * Use always serial for U-Boot console 875 */ 876 int overwrite_console(void) 877 { 878 return 1; 879 } 880 881 int board_init(void) 882 { 883 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 884 885 clrsetbits_le32(&iomuxc_regs->gpr[1], 886 IOMUXC_GPR1_OTG_ID_MASK, 887 IOMUXC_GPR1_OTG_ID_GPIO1); 888 889 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); 890 891 /* address of boot parameters */ 892 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 893 894 #ifdef CONFIG_MXC_SPI 895 setup_spi(); 896 #endif 897 imx_iomux_v3_setup_multiple_pads( 898 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 899 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 900 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 901 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 902 903 #ifdef CONFIG_CMD_SATA 904 setup_sata(); 905 #endif 906 907 return 0; 908 } 909 910 int checkboard(void) 911 { 912 if (gpio_get_value(WL12XX_WL_IRQ_GP)) 913 puts("Board: Nitrogen6X\n"); 914 else 915 puts("Board: SABRE Lite\n"); 916 917 return 0; 918 } 919 920 struct button_key { 921 char const *name; 922 unsigned gpnum; 923 char ident; 924 }; 925 926 static struct button_key const buttons[] = { 927 {"back", IMX_GPIO_NR(2, 2), 'B'}, 928 {"home", IMX_GPIO_NR(2, 4), 'H'}, 929 {"menu", IMX_GPIO_NR(2, 1), 'M'}, 930 {"search", IMX_GPIO_NR(2, 3), 'S'}, 931 {"volup", IMX_GPIO_NR(7, 13), 'V'}, 932 {"voldown", IMX_GPIO_NR(4, 5), 'v'}, 933 }; 934 935 /* 936 * generate a null-terminated string containing the buttons pressed 937 * returns number of keys pressed 938 */ 939 static int read_keys(char *buf) 940 { 941 int i, numpressed = 0; 942 for (i = 0; i < ARRAY_SIZE(buttons); i++) { 943 if (!gpio_get_value(buttons[i].gpnum)) 944 buf[numpressed++] = buttons[i].ident; 945 } 946 buf[numpressed] = '\0'; 947 return numpressed; 948 } 949 950 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 951 { 952 char envvalue[ARRAY_SIZE(buttons)+1]; 953 int numpressed = read_keys(envvalue); 954 setenv("keybd", envvalue); 955 return numpressed == 0; 956 } 957 958 U_BOOT_CMD( 959 kbd, 1, 1, do_kbd, 960 "Tests for keypresses, sets 'keybd' environment variable", 961 "Returns 0 (true) to shell if key is pressed." 962 ); 963 964 #ifdef CONFIG_PREBOOT 965 static char const kbd_magic_prefix[] = "key_magic"; 966 static char const kbd_command_prefix[] = "key_cmd"; 967 968 static void preboot_keys(void) 969 { 970 int numpressed; 971 char keypress[ARRAY_SIZE(buttons)+1]; 972 numpressed = read_keys(keypress); 973 if (numpressed) { 974 char *kbd_magic_keys = getenv("magic_keys"); 975 char *suffix; 976 /* 977 * loop over all magic keys 978 */ 979 for (suffix = kbd_magic_keys; *suffix; ++suffix) { 980 char *keys; 981 char magic[sizeof(kbd_magic_prefix) + 1]; 982 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); 983 keys = getenv(magic); 984 if (keys) { 985 if (!strcmp(keys, keypress)) 986 break; 987 } 988 } 989 if (*suffix) { 990 char cmd_name[sizeof(kbd_command_prefix) + 1]; 991 char *cmd; 992 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); 993 cmd = getenv(cmd_name); 994 if (cmd) { 995 setenv("preboot", cmd); 996 return; 997 } 998 } 999 } 1000 } 1001 #endif 1002 1003 #ifdef CONFIG_CMD_BMODE 1004 static const struct boot_mode board_boot_modes[] = { 1005 /* 4 bit bus width */ 1006 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 1007 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, 1008 {NULL, 0}, 1009 }; 1010 #endif 1011 1012 int misc_init_r(void) 1013 { 1014 #ifdef CONFIG_PREBOOT 1015 preboot_keys(); 1016 #endif 1017 1018 #ifdef CONFIG_CMD_BMODE 1019 add_board_boot_modes(board_boot_modes); 1020 #endif 1021 setenv_hex("reset_cause", get_imx_reset_cause()); 1022 return 0; 1023 } 1024