1/* 2 * Copyright (C) 2013 Boundary Devices 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Device Configuration Data (DCD) 7 * 8 * Each entry must have the format: 9 * Addr-type Address Value 10 * 11 * where: 12 * Addr-type register length (1,2 or 4 bytes) 13 * Address absolute address of the register 14 * value value to be stored in the register 15 */ 16 17/* 18 * DDR3 settings 19 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), 20 * memory bus width: 64 bits x16/x32/x64 21 * MX6DL ddr is limited to 800 MHz(400 MHz clock) 22 * memory bus width: 64 bits x16/x32/x64 23 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) 24 * memory bus width: 32 bits x16/x32 25 */ 26DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 27DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 28DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 29DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 30DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 31DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 32DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 33DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 34 35DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 36DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 37DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 38DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 39DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 40DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 41DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 42DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 43DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 44/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 45DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 46 47DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 48DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 49DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 50DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 51DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 52DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 53DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 54DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 55 56DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 57DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 58DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 59DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 60 61DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 62DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 63DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 64 65DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 66DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 67 68/* (differential input) */ 69DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 70/* (differential input) */ 71DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 72/* disable ddr pullups */ 73DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 74DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 75/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 76DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 77 78/* Read data DQ Byte0-3 delay */ 79DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 80DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 81DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 82DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 83DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 84DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 85DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 86DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 87 88/* 89 * MDMISC mirroring interleaved (row/bank/col) 90 */ 91DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 92 93/* 94 * MDSCR con_req 95 */ 96DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 97