1/*
2 * Copyright (C) 2013 Boundary Devices
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not write to the Free Software
19 * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
20 * MA 02110-1301 USA
21 *
22 * Device Configuration Data (DCD)
23 *
24 * Each entry must have the format:
25 * Addr-type           Address        Value
26 *
27 * where:
28 *      Addr-type register length (1,2 or 4 bytes)
29 *      Address   absolute address of the register
30 *      value     value to be stored in the register
31 */
32
33/*
34 * DDR3 settings
35 * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
36 *	   memory bus width: 64 bits	x16/x32/x64
37 * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
38 *	   memory bus width: 64 bits	x16/x32/x64
39 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
40 *	   memory bus width: 32 bits	x16/x32
41 */
42DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
43DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
44DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
45DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
46DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
47DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
48DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
49DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
50
51DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
52DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
53DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
54DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
55DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
56DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
57DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
58DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
59DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
60/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
61DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
62
63DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
64DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
65DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
66DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
67DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
68DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
69DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
70DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
71
72DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
73DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
74DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
75DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
76
77DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030
78DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
79DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
80
81DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
82DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
83
84/* (differential input) */
85DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
86/* (differential input) */
87DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
88/* disable ddr pullups */
89DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
90DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
91/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
92DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
93
94/* Read data DQ Byte0-3 delay */
95DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
96DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
97DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
98DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
99DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
100DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
101DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
102DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
103
104/*
105 * MDMISC	mirroring	interleaved (row/bank/col)
106 */
107DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
108
109/*
110 * MDSCR	con_req
111 */
112DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
113