1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2013 Boundary Devices 4 * 5 * Device Configuration Data (DCD) 6 * 7 * Each entry must have the format: 8 * Addr-type Address Value 9 * 10 * where: 11 * Addr-type register length (1,2 or 4 bytes) 12 * Address absolute address of the register 13 * value value to be stored in the register 14 */ 15 16/* 17 * DDR3 settings 18 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), 19 * memory bus width: 64 bits x16/x32/x64 20 * MX6DL ddr is limited to 800 MHz(400 MHz clock) 21 * memory bus width: 64 bits x16/x32/x64 22 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) 23 * memory bus width: 32 bits x16/x32 24 */ 25DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 26DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 27DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 28DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 29DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 30DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 31DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 32DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 33 34DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 35DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 36DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 37DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 38DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 39DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 40DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 41DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 42DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 43/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 44DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 45 46DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 47DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 48DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 49DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 50DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 51DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 52DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 53DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 54 55DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 56DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 57DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 58DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 59 60DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 61DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 62DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 63 64DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 65DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 66 67/* (differential input) */ 68DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 69/* (differential input) */ 70DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 71/* disable ddr pullups */ 72DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 73DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 74/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 75DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 76 77/* Read data DQ Byte0-3 delay */ 78DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 79DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 80DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 81DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 82DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 83DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 84DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 85DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 86 87/* 88 * MDMISC mirroring interleaved (row/bank/col) 89 */ 90DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 91 92/* 93 * MDSCR con_req 94 */ 95DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 96