1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * mux.c 4 * 5 * (C) Copyright 2016 6 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 7 * 8 * Based on: 9 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 10 */ 11 12 #include <common.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/arch/hardware.h> 15 #include <asm/arch/mux.h> 16 #include <asm/io.h> 17 #include <i2c.h> 18 #include "board.h" 19 20 static struct module_pin_mux uart0_pin_mux[] = { 21 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_RXD */ 22 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */ 23 {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_CTS */ 24 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)}, /* UART0_RTS */ 25 {-1}, 26 }; 27 28 static struct module_pin_mux uart1_pin_mux[] = { 29 {OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART1_RXD */ 30 {OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)}, /* UART1_TXD */ 31 {OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART1_CTS */ 32 {OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)}, /* UART1_RTS */ 33 {-1}, 34 }; 35 36 static struct module_pin_mux uart2_pin_mux[] = { 37 {OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* UART2_RXD */ 38 {OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)}, /* UART2_TXD */ 39 {-1}, 40 }; 41 42 static struct module_pin_mux spi1_pin_mux[] = { 43 {OFFSET(mcasp0_aclkx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_SCLK */ 44 {OFFSET(mcasp0_fsx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D0 */ 45 {OFFSET(mcasp0_axr0), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D1 */ 46 {OFFSET(mcasp0_ahclkr), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_CS0 */ 47 {-1}, 48 }; 49 50 static struct module_pin_mux uart4_pin_mux[] = { 51 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ 52 {OFFSET(gpmc_wpn), (MODE(6) | PULLUP_EN)}, /* UART4_TXD */ 53 {-1}, 54 }; 55 56 static struct module_pin_mux mmc0_pin_mux[] = { 57 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT3 */ 58 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT2 */ 59 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT1 */ 60 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_DAT0 */ 61 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 62 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* MMC0_CMD */ 63 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDDIS)}, /* MMC0_CD */ 64 {-1}, 65 }; 66 67 static struct module_pin_mux mmc1_pin_mux[] = { 68 {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ 69 {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ 70 {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ 71 {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ 72 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ 73 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ 74 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ 75 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ 76 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUDDIS)}, /* MMC1_CLK */ 77 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ 78 {-1}, 79 }; 80 81 static struct module_pin_mux mmc2_pin_mux[] = { 82 {OFFSET(gpmc_ad12), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT0 */ 83 {OFFSET(gpmc_ad13), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT1 */ 84 {OFFSET(gpmc_ad14), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT2 */ 85 {OFFSET(gpmc_ad15), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT3 */ 86 {OFFSET(gpmc_csn3), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CMD */ 87 {OFFSET(gpmc_clk), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CLK */ 88 {-1}, 89 }; 90 static struct module_pin_mux i2c0_pin_mux[] = { 91 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_DATA */ 92 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_SCLK */ 93 {-1}, 94 }; 95 96 static struct module_pin_mux gpio0_7_pin_mux[] = { 97 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUP_EN)}, /* GPIO0_7 */ 98 {-1}, 99 }; 100 101 static struct module_pin_mux jtag_pin_mux[] = { 102 {OFFSET(xdma_event_intr0), (MODE(6) | RXACTIVE | PULLUDDIS)}, 103 {OFFSET(xdma_event_intr1), (MODE(6) | RXACTIVE | PULLUDDIS)}, 104 {OFFSET(nresetin_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, 105 {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)}, 106 {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)}, 107 {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)}, 108 {OFFSET(tdo), (MODE(0) | PULLUP_EN)}, 109 {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)}, 110 {OFFSET(ntrst), (MODE(0) | RXACTIVE)}, 111 {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)}, 112 {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)}, 113 {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)}, 114 {OFFSET(rsvd2), (MODE(0) | PULLUP_EN)}, 115 {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, 116 {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)}, 117 {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)}, 118 {OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)}, 119 {OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS)}, 120 {-1}, 121 }; 122 123 static struct module_pin_mux gpio_pin_mux[] = { 124 {OFFSET(gpmc_ad8), (MODE(7) | PULLUDDIS)}, /* gpio0[22] - LED_PWR_BL (external pull-down) */ 125 {OFFSET(gpmc_ad9), (MODE(7) | PULLUDDIS)}, /* gpio0[23] - LED_PWR_RD (external pull-down) */ 126 {OFFSET(gpmc_ad10), (MODE(7) | PULLUDDIS)}, /* gpio0[26] - LED_LAN_RD (external pull-down) */ 127 {OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)}, /* gpio0[27] - #WIFI_RST (external pull-down) */ 128 {OFFSET(gpmc_a0), (MODE(7) | PULLUDDIS)}, /* gpio1[16] - WIFI_REGEN */ 129 {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS)}, /* gpio1[17] - LED_LAN_BL */ 130 {OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS)}, /* gpio1[18] - LED_Cloud_BL */ 131 {OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS)}, /* gpio1[19] - LED_PWM as GPIO */ 132 {OFFSET(gpmc_a4), (MODE(7))}, /* gpio1[20] - #eMMC_RST */ 133 {OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)}, /* gpio1[21] - #Z-Wave_RST */ 134 {OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)}, /* gpio1[22] - ENOC_RST */ 135 {OFFSET(gpmc_a7), (MODE(7) | PULLUP_EN)}, /* gpio1[23] - WIFI_MODE */ 136 {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[24] - #BIDCOS_RST */ 137 {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[25] - USR_BUTTON */ 138 {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[26] - #USB1_OC */ 139 {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[27] - BIDCOS_PROG */ 140 {OFFSET(gpmc_be1n), (MODE(7) | PULLUP_EN)}, /* gpio1[28] - ZIGBEE_PC7 */ 141 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUDDIS)}, /* gpio1[29] - RESET_BUTTON */ 142 {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS)}, /* gpio2[2] - LED_Cloud_RD */ 143 {OFFSET(gpmc_oen_ren), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* gpio2[3] - #WIFI_POR */ 144 {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, /* gpio2[4] - N/C */ 145 {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)}, /* gpio2[5] - EEPROM_WP */ 146 {OFFSET(lcd_data0), (MODE(7) | PULLUDDIS)}, /* gpio2[6] */ 147 {OFFSET(lcd_data1), (MODE(7) | PULLUDDIS)}, /* gpio2[7] */ 148 {OFFSET(lcd_data2), (MODE(7) | PULLUDDIS)}, /* gpio2[8] */ 149 {OFFSET(lcd_data3), (MODE(7) | PULLUDDIS)}, /* gpio2[9] */ 150 {OFFSET(lcd_data4), (MODE(7) | PULLUDDIS)}, /* gpio2[10] */ 151 {OFFSET(lcd_data5), (MODE(7) | PULLUDDIS)}, /* gpio2[11] */ 152 {OFFSET(lcd_data6), (MODE(7) | PULLUDDIS)}, /* gpio2[12] */ 153 {OFFSET(lcd_data7), (MODE(7) | PULLUDDIS)}, /* gpio2[13] */ 154 {OFFSET(lcd_data8), (MODE(7) | PULLUDDIS)}, /* gpio2[14] */ 155 {OFFSET(lcd_data9), (MODE(7) | PULLUDDIS)}, /* gpio2[15] */ 156 {OFFSET(lcd_data10), (MODE(7) | PULLUDDIS)}, /* gpio2[16] */ 157 {OFFSET(lcd_data11), (MODE(7) | PULLUDDIS)}, /* gpio2[17] */ 158 {OFFSET(lcd_data12), (MODE(7) | PULLUDDIS)}, /* gpio0[8] */ 159 {OFFSET(lcd_data13), (MODE(7) | PULLUDDIS)}, /* gpio0[9] */ 160 {OFFSET(lcd_data14), (MODE(7) | PULLUDDIS)}, /* gpio0[10] */ 161 {OFFSET(lcd_data15), (MODE(7) | PULLUDDIS)}, /* gpio0[11] */ 162 {OFFSET(lcd_vsync), (MODE(7) | PULLUDDIS)}, /* gpio2[22] */ 163 {OFFSET(lcd_hsync), (MODE(7) | PULLUDDIS)}, /* gpio2[23] */ 164 {OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)}, /* gpio2[24] */ 165 {OFFSET(lcd_ac_bias_en), (MODE(7) | PULLUDDIS)},/* gpio2[25] */ 166 {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS)}, /* gpio0[4] */ 167 {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, /* gpio0[5] */ 168 {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS)}, /* gpio3[18] - #ZIGBEE_RST */ 169 {OFFSET(mcasp0_fsr), (MODE(7)) | PULLUDDIS}, /* gpio3[19] - ZIGBEE_BOOT */ 170 {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, /* gpio3[19] - ZIGBEE_BOOT */ 171 {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE | PULLUP_EN)},/* gpio3[21] - ZIGBEE_PC5 */ 172 {-1}, 173 }; 174 175 static struct module_pin_mux mii1_pin_mux[] = { 176 {OFFSET(mii1_col), MODE(0) | RXACTIVE}, 177 {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, 178 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, 179 {OFFSET(mii1_txen), MODE(0)}, 180 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, 181 {OFFSET(mii1_txd3), MODE(0)}, 182 {OFFSET(mii1_txd2), MODE(0)}, 183 {OFFSET(mii1_txd1), MODE(0) | RXACTIVE}, 184 {OFFSET(mii1_txd0), MODE(0) | RXACTIVE}, 185 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, 186 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, 187 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, 188 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, 189 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, 190 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, 191 {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, 192 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, 193 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, 194 {-1}, 195 }; 196 197 static struct module_pin_mux pwm_pin_mux[] = { 198 {OFFSET(gpmc_a3), (MODE(6) | PULLUDDIS)}, 199 {-1}, 200 }; 201 202 void enable_uart0_pin_mux(void) 203 { 204 configure_module_pin_mux(uart0_pin_mux); 205 } 206 207 void enable_uart1_pin_mux(void) 208 { 209 configure_module_pin_mux(uart1_pin_mux); 210 } 211 212 void enable_uart2_pin_mux(void) 213 { 214 configure_module_pin_mux(uart2_pin_mux); 215 } 216 217 void enable_uart3_pin_mux(void) 218 { 219 } 220 221 void enable_uart4_pin_mux(void) 222 { 223 configure_module_pin_mux(uart4_pin_mux); 224 } 225 226 void enable_uart5_pin_mux(void) 227 { 228 } 229 230 void enable_i2c0_pin_mux(void) 231 { 232 configure_module_pin_mux(i2c0_pin_mux); 233 } 234 235 void enable_shc_board_pwm_pin_mux(void) 236 { 237 configure_module_pin_mux(pwm_pin_mux); 238 } 239 240 void enable_shc_board_pin_mux(void) 241 { 242 /* Do board-specific muxes. */ 243 if (board_is_c3_sample() || board_is_series()) { 244 configure_module_pin_mux(mii1_pin_mux); 245 configure_module_pin_mux(mmc0_pin_mux); 246 configure_module_pin_mux(mmc1_pin_mux); 247 configure_module_pin_mux(mmc2_pin_mux); 248 configure_module_pin_mux(i2c0_pin_mux); 249 configure_module_pin_mux(gpio0_7_pin_mux); 250 configure_module_pin_mux(gpio_pin_mux); 251 configure_module_pin_mux(uart1_pin_mux); 252 configure_module_pin_mux(uart2_pin_mux); 253 configure_module_pin_mux(uart4_pin_mux); 254 configure_module_pin_mux(spi1_pin_mux); 255 configure_module_pin_mux(jtag_pin_mux); 256 } else { 257 puts("Unknown board, cannot configure pinmux."); 258 hang(); 259 } 260 } 261